Texas Instruments DLP® LightCrafter™ 4500 DLPLCR4500EVM DLPLCR4500EVM 데이터 시트
제품 코드
DLPLCR4500EVM
DLPS028A – APRIL 2013 – REVISED MAY 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by the
data sheet is achieved when operating the device within the limits defined by the
. No
level of performance is implied when operating the device above or below the
limits.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
ELECTRICAL
VREF
LVCMOS interface supply voltage
(1)
1.6
1.9
2.0
V
VCC
LVCMOS logic supply voltage
(1)
2.375
2.500
2.625
V
VOFFSET
Mirror electrode and HVCMOS supply voltage
(1) (2)
8.25
8.500
8.75
V
VBIAS
Mirror electrode voltage
(1) (2)
15.5
16 .0
16.5
V
VRESET
Mirror electrode voltage
(1)
– 9.5
–10.0
–10.5
V
Delta supply voltage |VBIAS – VOFFSET|
(2)
8.75
V
0.4 ×
0.7 ×
V
T+
Positive-going threshold voltage
V
VREF
VREF
0.3 ×
0.6 ×
V
T–
Negative-going threshold voltage
V
VREF
VREF
0.1 ×
0.4 ×
V
hys
Hysteresis voltage (V
T+
– V
T–
)
V
VREF
VREF
f
DCLK
DCLK clock frequency
80
120
MHz
MECHANICAL
Uniformly distributed
Static load applied to the package electrical
across the three datum-A
110
N
connector area
(3)
areas and the datum-E
Package FQE
area.
Static load applied to the DMD mounting area
(3)
110
N
Load applied to the thermal interface area
(3)
62
N
Package FQD
Uniformly distributed over
Load applied to the electrical interface areas
(3)
55
N
2 areas
ENVIRONMENTAL
Operating Case Temperature
See
(4)
.
26
See
(4)
.
°C
Operating Humidity
(4)
non-condensing
60
See
(4)
% RH
Operating Device Temperature Gradient
(5)
10
°C
Operating Landed Duty-Cycle
(4) (6)
See
(4)
25
See
(4)
%
(1)
Voltages VCC, VREF, VOFFSET, VBIAS, VRESET are required for proper DMD operation. All voltages referenced to VSS (ground).
(2)
Exceeding the recommended voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(3)
See System Interface Load diagrams on the next pages.
(4)
Optimal, long-term performance of the Digital Micromirror Device (DMD) can be affected by various application parameters, including
illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), case
temperature, ambient humidity (storage and operating), and power on/off duty cycle. TI recommends that application-specific effects be
considered as early as possible in the design cycle. Contact your local TI representative for additional information related to optimizing
the DMD performance.
illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), case
temperature, ambient humidity (storage and operating), and power on/off duty cycle. TI recommends that application-specific effects be
considered as early as possible in the design cycle. Contact your local TI representative for additional information related to optimizing
the DMD performance.
(5)
As measured between any two points on or within the package including the mirror array. See the Thermal Characteristics for
information related to calculating the micromirror array temperature.
information related to calculating the micromirror array temperature.
(6)
Landed Duty-Cycle refers to the percentage of time an individual micromirror spends landed in one state (+12° or -12°) versus the other
state (-12° or +12°).
state (-12° or +12°).
Copyright © 2013, Texas Instruments Incorporated
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