Texas Instruments TPS43061 Evaluation Module TPS43061EVM-198 TPS43061EVM-198 데이터 시트
제품 코드
TPS43061EVM-198
Time = 400 ns/div
1
0
.0
V
/d
iv
1
0
.0
V
/d
iv
C2: HDRV
C1: SW
5
.0
0
V
/d
iv
C3: LDRV
Time = 5.00 ms/div
5
.0
0
V
/d
iv
5
.0
0
V
/d
iv
C2: VCC
C3: V
OUT
5
.0
0
V
/d
iv
C1: V
IN
5
.0
0
V
/d
iv
C4: PGOOD
Time = 200 ms/div
5
.0
0
V
/d
iv
5
.0
0
V
/d
iv
C2: VCC
C3: V
OUT
5
.0
0
V
/d
iv
C1: EN
5
.0
0
V
/d
iv
C4: PGOOD
Test Setup and Results
2.8
Shutdown
The shutdown waveforms are shown in
and
. In
the input voltage is
removed, and when the input falls below the undervoltage lockout threshold set by the EN resistor divider,
the TPS43061 shuts down, PGOOD is pulled low and the output falls to ground. The output has a 2-A
resistive load.
the TPS43061 shuts down, PGOOD is pulled low and the output falls to ground. The output has a 2-A
resistive load.
In
the input voltage is held at 9 V with no load and EN is shorted to ground. When EN is
grounded, the TPS43061 is disabled, PGOOD is pulled low and the output voltage discharges to VIN.
Figure 14. Shutdown Relative to V
IN
Figure 15. Shutdown Relative to EN
2.9
Gate-Drive Signals
In
the gate-drive signals for the high-side and low-side FETs can be seen with the switching
node are shown. The input voltage is 9 V and the output has a 2-A load.
Figure 16. Gate-Drive Signals
10
Using the TPS43061 Boost Evaluation Module (EVM)
SLVU799A – November 2012 – Revised March 2013
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