Texas Instruments TPS43061 Evaluation Module TPS43061EVM-198 TPS43061EVM-198 데이터 시트
제품 코드
TPS43061EVM-198
UVLO_ H
EN _ DIS
UVLO_ L
STOP
EN _ DIS
UVLO _ H
EN _ pup
EN _ hys
R
V
R
V
V
R
I
I
u
u
EN _ DIS
START
STOP
EN _ ON
UVLO_ H
EN _ DIS
EN _ pup
EN _ hys
EN _ ON
V
V
V
V
R
V
I
1
I
V
§
·
u ¨
¸
¨
¸
©
¹
§
·
u ¨
¸
¨
¸
©
¹
Test Setup and Results
1.3.4
Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R3 and R4. The EVM is set for a start
voltage of 5.34 V and stop voltage of 4.31 V using R3 = 221 k
voltage of 5.34 V and stop voltage of 4.31 V using R3 = 221 k
Ω
and R4 = 59.0 k
Ω
. Use
and
to calculate the required resistor values for R3 and R4 respectively for different start and stop
voltages. The typical values of the constants in the two equations are as follows: V
EN_DIS
= 1.14 V, V
EN_ON
=
1.21 V, I
EN_pup
= 1.8 µA, and I
EN_hys
= 3.2 µA.
(5)
(6)
1.3.5
Input Voltage Rails
The EVM is designed to accommodate different input voltage levels for the power stage and control logic.
During normal operation, the VIN inputs are the same with R11 shorted. The single input voltage is
supplied to J6. If desired, the two input voltage rails may be separated by removing R11. The control logic
input voltage can be supplied to J4 and the power stage input voltage to J6.
During normal operation, the VIN inputs are the same with R11 shorted. The single input voltage is
supplied to J6. If desired, the two input voltage rails may be separated by removing R11. The control logic
input voltage can be supplied to J4 and the power stage input voltage to J6.
1.3.6
Further Modification
Be aware, changing the input and output of conditions of the EVM will impact the design. It may also be
necessary to modify the inductor, output capacitor and compensation components for the desired
performance in the application. Additionally the CSD86330Q3D power block limits the output voltage to a
maximum recommend output voltage of 22 V. Please see the data sheet or the excel design spreadsheet
located in the product folder for details.
necessary to modify the inductor, output capacitor and compensation components for the desired
performance in the application. Additionally the CSD86330Q3D power block limits the output voltage to a
maximum recommend output voltage of 22 V. Please see the data sheet or the excel design spreadsheet
located in the product folder for details.
2
Test Setup and Results
This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up and shutdown.
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up and shutdown.
2.1
Input/Output Connections
This EVM includes input/output connectors and test points as shown in
. A power supply capable
of supplying at least 6 A must be connected to J6 through a pair of 20-AWG wires. The load must be
connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be 2 A. Wire
lengths must be minimized to reduce losses in the wires. If any modification is done to the EVM design, an
input supply and load rated for the new design are required. Test point TP8 provides a place to monitor
the V
connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be 2 A. Wire
lengths must be minimized to reduce losses in the wires. If any modification is done to the EVM design, an
input supply and load rated for the new design are required. Test point TP8 provides a place to monitor
the V
IN
input voltages with TP9 providing a convenient ground reference. TP3 is used to monitor the output
voltage with TP4 as the ground reference.
Table 3. EVM Connectors and Test points
Reference Designator
Function
J1
2-pin header for V
OUT
voltage connections
J2
V
OUT
, 15 V at 2-A maximum
J3
2-pin header for GND connections
J4
2-pin header for optional V
BIAS
input voltage connections (see
)
J5
2-pin header for V
IN
input voltage connections
J6
V
IN
(see
for V
IN
range)
J7
2-pin header for GND connections
JP1
3-pin header for EN jumper. Install jumper from pins 1-2 to enable or pins 2-3 to disable.
5
SLVU799A – November 2012 – Revised March 2013
Using the TPS43061 Boost Evaluation Module (EVM)
Copyright © 2012–2013, Texas Instruments Incorporated