Texas Instruments TAS2505 Evaluation Module TAS2505EVM TAS2505EVM 데이터 시트
제품 코드
TAS2505EVM
STO
STA
STA
STO
SDA
SCL
t
BUF
t
LOW
t
SU;STA
t
HIGH
t
HD;STA
t
r
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
f
T0295-02
SLAS778A – FEBRUARY 2013 – REVISED FEBRUARY 2013
3.5.5
I
2
C Interface Timing
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
PARAMETER
Standard-Mode
Fast-Mode
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
f
SCL
SCL clock frequency
0
100
0
400
kHz
Hold time (repeated) START condition.
t
HD;STA
After this period, the first clock pulse is
4
0.8
μ
s
generated.
t
LOW
LOW period of the SCL clock
4.7
1.3
μ
s
t
HIGH
HIGH period of the SCL clock
4
0.6
μ
s
Setup time for a repeated START
t
SU;STA
4.7
0.8
μ
s
condition
t
HD;DAT
Data hold time: For I
2
C bus devices
0
3.45
0
0.9
μ
s
t
SU;DAT
Data setup time
250
100
ns
t
r
SDA and SCL rise time
1000
20 + 0.1 C
b
300
ns
t
f
SDA and SCL fall time
300
20 + 0.1 C
b
300
ns
t
SU;STO
Set-up time for STOP condition
4
0.8
μ
s
Bus free time between a STOP and
t
BUF
4.7
1.3
μ
s
START condition
C
b
Capacitive load for each bus line
400
400
pF
Figure 3-5. I
2
C Interface Timing
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
13
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