Texas Instruments 2A, SWIFT (tm) Converter Evaluation Module TPS54233EVM-373 TPS54233EVM-373 데이터 시트
제품 코드
TPS54233EVM-373
V
IN
V
OUT
V
OUT
PH
3
Board Layout
3.1
Layout
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Board Layout
Figure 10. TPS54233EVM-373 Start-up Relative to Enable
Figure 11. TPS54233EVM-373 ECO_MODE™ Operation
This section provides a description of the TPS54233EVM-373, board layout, and layer illustrations.
The board layout for the TPS54233EVM-373 is shown in
through
. The topside layer of
the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54233 and a large area filled with ground. The bottom layer
contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces
are connected with multiple vias placed around the board including ten vias directly under the TPS54233
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces
are connected with multiple vias placed around the board including ten vias directly under the TPS54233
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
SLVU264 – November 2008
TPS54233EVM-373 2-A, SWIFT™ Regulator Evaluation Module
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