Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM 데이터 시트
제품 코드
MUXIT-EVM
Serializer Board
2-2
2.1
Serializer Board
The serializer board (P/N 6422795A) uses three SN65LVDS151 MuxIt
serializer-transmitter devices (U2–U4) and an SN65LVDS150 phase-locked
loop (PLL) frequency multiplier (U1) to convert parallel single-ended inputs to
a serialized LVDS link containing one or two data pairs and a clock pair. The
serializer board will be referred to as A1 and the deserializer board will be
referred to as A2 throughout this document to identify jumper, connector, test
point, and device references with the appropriate board. A block diagram and
photograph of the serializer board is provided in Figures 2–1 and 2–2.
serializer-transmitter devices (U2–U4) and an SN65LVDS150 phase-locked
loop (PLL) frequency multiplier (U1) to convert parallel single-ended inputs to
a serialized LVDS link containing one or two data pairs and a clock pair. The
serializer board will be referred to as A1 and the deserializer board will be
referred to as A2 throughout this document to identify jumper, connector, test
point, and device references with the appropriate board. A block diagram and
photograph of the serializer board is provided in Figures 2–1 and 2–2.
2.1.1
Clock and Data Input Signals
The clock reference into the serializer board can be either single-ended
(LVTTL) or differential (LVDS). The inputs A1:J3 and A1:J4 are terminated (50
ohms) for a differential input, but a single-ended input can be applied to A1:J3
when A1:JMP-1 is installed. This jumper connects the VT signal out of the PLL
(pin 4 of A1:U1) to the CRI– input (pin 3 of A1:U1), biasing the unused A1:J4
input to VCC/2. Note that the VT signal cannot drive a 50
(LVTTL) or differential (LVDS). The inputs A1:J3 and A1:J4 are terminated (50
ohms) for a differential input, but a single-ended input can be applied to A1:J3
when A1:JMP-1 is installed. This jumper connects the VT signal out of the PLL
(pin 4 of A1:U1) to the CRI– input (pin 3 of A1:U1), biasing the unused A1:J4
input to VCC/2. Note that the VT signal cannot drive a 50
Ω
load, so when
providing a single-ended input with jumper A1:JMP-1 installed, resistor R2
must be removed to maintain the Vcc/2 reference level.
must be removed to maintain the Vcc/2 reference level.
The EVM also includes thirty jumper shorts that can be installed on the
serializer board data input pins (connectors A1:P1–P3) if the user wants to
apply static inputs (fixed logic 1 or 0). Each input connector is a 3
serializer board data input pins (connectors A1:P1–P3) if the user wants to
apply static inputs (fixed logic 1 or 0). Each input connector is a 3
×
10 header.
The center pins of each connector are connected to the input pins of a
SN65LVDS151 serializer-transmitter. A1:P1 is connected to A1:U2, A1:P2 is
connected to A1:U3, and A1:P3 is connected to A1:U4. The row of pins near
the center of the board is connected to VCC, and the row nearest the edge of
the board is connected to GND. These connections are marked on the boards.
SN65LVDS151 serializer-transmitter. A1:P1 is connected to A1:U2, A1:P2 is
connected to A1:U3, and A1:P3 is connected to A1:U4. The row of pins near
the center of the board is connected to VCC, and the row nearest the edge of
the board is connected to GND. These connections are marked on the boards.
In addition to static inputs, external devices can also drive the data inputs.
When a 5 V device supplies TTL inputs, a 5-V bias (V
When a 5 V device supplies TTL inputs, a 5-V bias (V
CC)
needs to be provided
to the serializer board at Test Point 2 (A1:TP-2) and the jumper short at
A1:JMP-5 moved to the External VCC5 position.
A1:JMP-5 moved to the External VCC5 position.
2.1.2
Output Signals
The output signals generated by the serializer board are LVDS pairs: LCO
±
(link clock output), CASCADE_DO
±
(cascade data output), and SERIAL_DO
±
(serial data output). Both LCO and CASCADE_DO are outputs of A1:U3 and
SERIAL_DO is output from A1:U4.
SERIAL_DO is output from A1:U4.
2.1.3
Power Supply
The standard method for providing power to the boards is via J1 (the
compression terminal) located at the top of each board. 3.3 Vdc is applied to
the red terminal (labeled VCC) and GND is applied to the black terminal
(labeled GND). When the two boards are connected using the 12-pin adapter
header, the boards can be powered using a single 3.3-Vdc supply. The power
can be applied to J1 on just one board, either serializer or deserializer, and the
compression terminal) located at the top of each board. 3.3 Vdc is applied to
the red terminal (labeled VCC) and GND is applied to the black terminal
(labeled GND). When the two boards are connected using the 12-pin adapter
header, the boards can be powered using a single 3.3-Vdc supply. The power
can be applied to J1 on just one board, either serializer or deserializer, and the