Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM 데이터 시트
제품 코드
MUXIT-EVM
Parallel Operation Using Two LVDS Data Pairs
4-10
to eight) and the effective throughput. For example, if 16-bit parallel input data
needs to be sampled at 10 MHz, then the data is equally divided between
A1:P2 and A1:P3. The clock reference is set to 10 MHz and the PLL multiplier
to 8. The result will be each LVDS data pair carrying 8 bits at 80 Mbps. The
amount of data transferred across the interface is now twice the signaling rate
(2
needs to be sampled at 10 MHz, then the data is equally divided between
A1:P2 and A1:P3. The clock reference is set to 10 MHz and the PLL multiplier
to 8. The result will be each LVDS data pair carrying 8 bits at 80 Mbps. The
amount of data transferred across the interface is now twice the signaling rate
(2
×
80 Mbps = 160 Mbps). The user is encouraged to evaluate the throughput
capabilities of MuxIt for different signaling rates. The input-to-output bit
mapping for the full 20 bits is shown in Table 4–3.
mapping for the full 20 bits is shown in Table 4–3.
Table 4–3. Input-to-Output Bit Mapping for 8- to 20-Parallel Bits Using Two LVDS Data
Lines
Inp ts
Outputs
Inputs
M = 4
M = 6
M = 8
M = 9
M = 10
DI–0 (A1:P2)
DO–6 (A2:P1)
DO–4 (A2:P1)
DO–2 (A2:P1)
DO–1 (A2:P1)
DO–0 (A2:P1)
DI–1 (A1:P2)
DO–7 (A2:P1)
DO–5 (A2:P1)
DO–3 (A2:P1)
DO–2 (A2:P1)
DO–1 (A2:P1)
DI–2 (A1:P2)
DO–8 (A2:P1)
DO–6 (A2:P1)
DO–4 (A2:P1)
DO–3 (A2:P1)
DO–2 (A2:P1)
DI–3 (A1:P2)
DO–9 (A2:P1)
DO–7 (A2:P1)
DO–5 (A2:P1)
DO–4 (A2:P1)
DO–3 (A2:P1)
DI–4 (A1:P2)
NA
DO–8 (A2:P1)
DO–6 (A2:P1)
DO–5 (A2:P1)
DO–4 (A2:P1)
DI–5 (A1:P2)
NA
DO–9 (A2:P1)
DO–7 (A2:P1)
DO–6 (A2:P1)
DO–5 (A2:P1)
DI–6 (A1:P2)
NA
NA
DO–8 (A2:P1)
DO–7 (A2:P1)
DO–6 (A2:P1)
DI–7 (A1:P2)
NA
NA
DO–9 (A2:P1)
DO–8 (A2:P1)
DO–7 (A2:P1)
DI–8 (A1:P2)
NA
NA
NA
DO–9 (A2:P1)
DO–8 (A2:P1)
DI–9 (A1:P2)
NA
NA
NA
NA
DO–9 (A2:P1)
DI–0 (A1:P3)
DO–6 (A2:P3)
DO–4 (A2:P3)
DO–2 (A2:P3)
DO–1 (A2:P3)
DO–0 (A2:P3)
DI–1 (A1:P3)
DO–7 (A2:P3)
DO–5 (A2:P3)
DO–3 (A2:P3)
DO–2 (A2:P3)
DO–1 (A2:P3)
DI–2 (A1:P3)
DO–8 (A2:P3)
DO–6 (A2:P3)
DO–4 (A2:P3)
DO–3 (A2:P3)
DO–2 (A2:P3)
DI–3 (A1:P3)
DO–9 (A2:P3)
DO–7 (A2:P3)
DO–5 (A2:P3)
DO–4 (A2:P3)
DO–3 (A2:P3)
DI–4 (A1:P3)
NA
DO–8 (A2:P3)
DO–6 (A2:P3)
DO–5 (A2:P3)
DO–4 (A2:P3)
DI–5 (A1:P3)
NA
DO–9 (A2:P3)
DO–7 (A2:P3)
DO–6 (A2:P3)
DO–5 (A2:P3)
DI–6 (A1:P3)
NA
NA
DO–8 (A2:P3)
DO–7 (A2:P3)
DO–6 (A2:P3)
DI–7 (A1:P3)
NA
NA
DO–9 (A2:P3)
DO–8 (A2:P3)
DO–7 (A2:P3)
DI–8 (A1:P3)
NA
NA
NA
DO–9 (P3)
DO–8 (A2:P3)
DI–9 (A1:P3)
NA
NA
NA
NA
DO–9 (A2:P3)
Again, this topology can support 8 to 20-bit parallel inputs, which are equally
divided between A1:P2 and A1:P3. The user needs to select the same PLL
multiplier ratio (M), between 4 and 10 on both boards. A total of three LVDS
lines are used; two for data and one for the clock timing reference.
divided between A1:P2 and A1:P3. The user needs to select the same PLL
multiplier ratio (M), between 4 and 10 on both boards. A total of three LVDS
lines are used; two for data and one for the clock timing reference.
This EVM is not designed for input widths greater than twenty bits. However,
MuxIt can transmit forty parallel inputs in the parallel operation if desired. Like
cascade operation, this topology would require four serializer-transmitters and
four receiver-deserializers. One pair of the LVDS lines is used to transmit a
clock signal and four LVDS pairs transmit the data. The transmission media
is reduced from 40 lines to 5 LVDS pairs (4 data and 1 clock).
MuxIt can transmit forty parallel inputs in the parallel operation if desired. Like
cascade operation, this topology would require four serializer-transmitters and
four receiver-deserializers. One pair of the LVDS lines is used to transmit a
clock signal and four LVDS pairs transmit the data. The transmission media
is reduced from 40 lines to 5 LVDS pairs (4 data and 1 clock).