Texas Instruments MuxIt-EVM Evaluation Module MUXIT-EVM MUXIT-EVM 데이터 시트
제품 코드
MUXIT-EVM
PC Board Layout Considerations
5-4
System Design Issues
Figure
5–2.
Illustrating Signal Delay Matching of the Deserializer Board
GND
GND
GND
GND
SN65L
VDS150
MuxIt PLL
Frequency Multiplier (U1)
CRI
MCO
+ –
LV
O
M1
M2
M3
M4
M5
EN
VT
LCRO
EN
BSEL
LCRO
– +
– +
SN65L
VDS152
MuxIt
Receiver–Deserializer (U2)
LV
I
DCO
DO–0 ... DO–9
+ –
+ –
– +
– +
CO EN
EN
CO
LCI
DI
MCI
SN65L
VDS152
MuxIt
Receiver–Deserializer (U3)
LV
I
DCO
DO–0 ... DO–9
+ –
+ –
– +
– +
CO EN
EN
CO
LCI
DI
MCI
SN65L
VDS152
MuxIt
Receiver–Deserializer (U4)
LV
I
DCO
DO–0 ... DO–9
+ –
+ –
– +
– +
CO EN
EN
CO
LCI
DI
MCI
T*
T*
RD–C
RD–B
RD–A
T*
T*
Data and Clock Input
t pd
(A2:MC1)
t pd
(A2:MC2)
t pd
(A2:MC3)
t pd
(CRI)
t pd
(SERIAL_DI)
J2
t pd
(LCI1)
t pd
(LCI2)
t pd
(LCI3)
T*
t pd
(CASCADE_DI)