Texas Instruments TLK10002SMAEVM Evaluation Module TLK10002SMAEVM TLK10002SMAEVM 데이터 시트
제품 코드
TLK10002SMAEVM
ON
+ 5V
+ 5V
GND
1p8V
REG
REG
1p5V
REG
REG
3p3V
REG
REG
EN
GND
GND
EN
GND
EN
EN
GND
EN
GND
EN
G
N
D
JITTER PLL
P 1
P 14
C 48
C 47
C 47
R 120
U 16
C 34
C 33
JM
P
9
U 12
R 86
JM
P
5
C 76
C 75
U 24
R
1
8
8
JMP 17
C 79
C 82
C
8
3
C 81
D 41
PLL_LOCK
G
N
D
VCC _IN
JM
P6
4
JMP 63
JMP 66
JMP 35
LE
CLK
MOSI
MISO
JMP 58
SPI
G
N
D
V
C
C
A
R 315
R
3
1
2
C
2
8
5
JMP 55
P
W
R
_
D
N
M
D
E
_
S
E
L
R
E
F
_
S
E
L
A
U
X
_
S
E
L
P
L
L
_
L
C
K
U 2
JITTER
CLEANER
CLEANER
AUXp
VDDRA_ HS
V
C
C
_
O
U
T
V
C
X
O
C 97
R
5
3
7
R
5
3
6
C 118
C 127
C 108
C 84
JMP 41
C 138
C 139
C 140
C
9
9
C
1
0
0
C
1
0
1
JM
P
7
3
C
1
2
3
C 124
C
1
2
5
JM
P
7
5
C
1
2
8
C
1
2
9
C
1
3
0
J
M
P
7
1
C
1
1
3
C
1
1
4
C
1
1
5
J
M
P
7
4
C
8
9
C
9
0
C
9
1
J
M
P
7
2
U 10
P 2
V
D
D
R
B
_
H
S
1
p
5
V
1
p
8
V
VDDO
V
D
D
R
B
_
L
S
V
D
D
R
A
_
L
S
1p0V
DIGITAL
DIGITAL
BJ
5V
PLUG
C 27
C 25
U 8
R69
R 52
C 20
C 18
JM
P
1
1p0V
ANALOG
ANALOG
JMP 3
VDDD
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
EN
DVDD
VDDA
VDDT
J
M
P
6
9
JM
P
7
0
J
M
P
6
7
JM
P
6
8
C 107
C117
C 80
C93
C
1
0
9
C
1
1
0
C
1
1
1
C
1
1
9
C
1
2
0
C
1
2
1
C
8
5
C
8
6
C
8
7
C
9
4
C
9
5
C
9
8
R
4
9
4
C293
C294
C294
R
4
9
5
C245
C243
C247
J42
J41
J 44
J71
J70
C
2
6
4
AUXn
C
2
7
0
C
2
6
8
C
2
6
9
C
2
7
1
U
5
7
U
7
0
U
7
3
U
7
9
U
7
6
J43
J 6
J 5
J 7
J8
J48
J 47
J 46
J45
JMP
76
J73
D
4
8
D
5
1
D
5
2
D
4
9
D
5
0
HSTXBn
HSTXBp
HSRXBp
HSRXBn
CLKOUTBn
U 1
J72
TLK10002 EVM
MOTHER BOARD
REV A
6
5
2
2
8
5
0
C
2
6
3
C
2
6
6
C
2
9
1
C
2
6
1
C
2
6
7
C
2
9
2
U
5
1
U
6
3
U
9
0
U
4
5
U
6
7
U
8
7
U
6
0
C
2
6
5
C
6
2
C
6
1
U
2
0
U
4
8
C
2
6
0
C
6
9
C
6
8
U
2
2
JMP
13
JMP 43
JMP 15
J6
5
JMP
52
SW 3
R
4
1
R
4
8
R
4
0
R
4
2
C
1
2
R
4
3
C 13
C 14
C 14
S
W
1
C
1
0
C
6
R 35
R 44
R 36
R 36
U 5
R
1
1
0
R
1
8
C
2
D 2
D 1
U 7
R 1
R 2
C
1
1
R475
R 474
R 474
R 15
R 14
R 14
C 4
R 11
R
5
R
3
R
8
R
2
8
R
2
7
R
2
6
R
2
5
C 7
JM
P
5
0
D 4
D 3
D 3
ONLINE
SUSPEND
SW 2
JMP
47
JMP 62
R
3
0
7
R
3
0
6
C
3
0
2
D
3
5
D
3
6
D
4
0
D
3
4
D
3
8
D
2
6
D
3
9
D
3
3
D
3
7
D
2
5
D
4
6
D
4
7
D
4
4
D
4
5
D
3
1
D
3
2
D
2
9
D
3
0
D
1
7
D
1
8
D
2
1
D
2
2
1
p
8
V
1
p
5
V
1
p
0
V
D
1
p
0
V
A
V
D
D
T
V
D
D
A
D
V
D
D
V
D
D
D
JC
_
V
C
C
A
J
C
_
V
C
X
O
J
C
_
V
C
C
_
O
U
T
J
C
_
V
C
C
_
IN
V
D
D
O
V
D
D
R
B
_
L
S
V
D
D
R
A
_
L
S
V
D
D
R
B
_
H
S
V
D
D
R
A
_
H
S
U42
U 41
U 64
D
4
3
D
4
2
SW 4
JMP 57
JMP 42
D 10 D 11
J
M
P
4
4
JMP 45
D
1
9
D
2
0
D
2
7
D
2
8
5
V
3
p
3
V
P
3
p
3
V
2
p
5
V
L
O
S
A
L
O
S
B
P
R
B
S
P
A
S
S
D
1
2
D
1
3
D
1
6
D
1
4
L
S
A
O
K
L
S
B
O
K
D
1
5
JM
P
4
8
G
N
D
L
S
O
K
O
U
T
A
L
S
O
K
O
U
T
B
G
N
D
JM
P
6
1
3 p3 V
JMP
60
U 39
JMP
53
STCI _VCC
GND
SCANCLK
SCANCFG
0
SCANIN
SCANOUT
SCANCFG
1
JMP 46
P
R
T
A
D
0
P
R
T
A
D
1
P
R
T
A
D
2
P
R
T
A
D
3
P
R
T
A
D
4
G
N
D
L
S
O
K
I
N
B
O
K
I
N
A
L
S
G
N
D
A
M
U
X
B
A
M
U
X
A
P
R
B
S
P
A
S
S
L
O
S
B
L
O
S
A
G
P
I
O
T
E
S
T
_
E
N
P
R
B
S
_
E
N
C
L
K
B
_
S
E
L
C
L
K
A
_
S
E
L
P
D
T
R
X
B
P
D
T
R
X
A
SCL
SDA
RATE _ SEL _ 1
RATE _ SEL _ 0
MOD DETECT
RX _ LOS
TX _FAULT
TX _DISABLE
JITTER CLEANER
RESET
GND
JC
RST
GND
RST
RST
BTN
RST
BTN
R
E
S
E
T
R
E
S
E
T
MAIN RESET
GND
MAIN
RST
RST
2
p
5
V
R
E
G
3
p
3
V
R
E
G
USB RESET
RST
RST
RST
GND
2p5 V
MDIOV
3p3 V
USB
M
D
IO
M
D
C
T
R
S
T
JTAG
GND
JTAG_V
3p3 V
R
S
T
R
S
T
STCI
USB
1
p
5
V
1
p
8
V
T
L
K
1
0
0
0
2
T
L
K
1
0
0
0
2
CLKOUTAp
CLKOUTAn
R
57
2
R
57
0
5
4 6
8
R
5
6 6
R
5
65
R
5
6 7
R
5
6 9
R
5
7 1
R
58
0
R
57
8
R
57
6
R
57
4
R
5
7 3
R
5
7
5
R
5
7 7
R
3
79
CLKOUTBp
C249
M
O
D
D
E
T
E
C
T
T
X
_
F
A
U
L
T
R
X
_
L
O
S
T
X
D
I
S
A
B
L
E
T
X
D
I
S
A
B
L
E
REFCLK1p
REF
REF
CLK1n
CLK0 p
REFCLK0n
G
N
D
I
2
C
D
IS
A
B
L
E
R
3
0
5
T
L
K
1
0
0
0
2
E
V
M
S
M
A
B
R
E
A
K
O
U
T
D
A
U
G
H
T
E
R
B
O
A
R
D
6
5
2
2
8
5
2
R
E
V
A
J4
J5
J6
OUTB0P
OUTB0 N
OUTB3 N
J16
OUTB 3P
J17
J35
OUTA0 N
J34
OUTA0 P
J31
OUTA1 N
J30
OUTA1 P
GND
JM
P
5
G
N
D
JMP2
LS_ OK_IN_A
LS_OK_OUT_A
LS_ OK_IN_B
LS_OK_OUT_ B
G
N
D
G
N
D
J2
J3
INB2P
J10
J11
INB2N
J8
J9
OUTB2N
J12
OUTB 2P
J13
J14
INB3P
J15
INB3 N
J33
INA0P
J32
INA0N
J23
OUTA3N
J22
OUTA3P
R
1
2
R
1
1
CHB _CLKOUTP
JMP1
CHB_ CLKOUTN
R1
8
R
1
7
R
33
R
3
4
I2
C
_
S
D
A
I2
C
_
S
C
L
J21
INA3P
J20
INA3N
R
19
R2
0
J25
INA2P
R2
3
R
2 4
J24
INA2N
J29
INA1P
J28
INA1 N
R2
9
R
30
J26
OUTA2P
J27
OUTA2N
J37
CHA _CLKOUTN
J36
CHA_ CLKOUTP
R
3
5
R
3 6
R
1
6
R
1
5
OUTB 1N
OUTB 1P
INB0N
INB0P
R2
R
1
MDC_ POST_ LS
MDIO _POST_LS
MDIO _PRE_LS
MDC_PRE _LS
JMP3
JMP4
INB1 N
INB1 P
R6
R5
J7
J19
J18
G
N
D
USB FOR
TLK10002 GUI
5 V
GND
SYSTEM BOARD THAT
NEEDS TO BE
OPTIMIZED
MDIO / MDC POST _LS
SIGNALS CONNECTED
TO SYSTEM BOARD
T
L
K
1
0
0
0
2
T
L
K
1
0
0
0
2
PRTAD
0
PRTAD
1
PRTAD
2
PRTAD
3
PRTAD
4
SET THE “PORT ADDR”
FIELD OF THE GUI TO
MATCH THE PRTAD [4:0]
OF THE SYSTEM BOARD
AND ENSURE IT IS
DIFFERENT THAN THE
PRTAD [4:0] OF THE EVM
MOTHER BOARD
M
D
C
M
D
IO
Test and Setup Configurations
Figure 7. Optimizing the High-Speed Link of a System Board Through the GUI
15
SLLU148
–
May 2011
TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated