Texas Instruments SN65HVD72EVM Evaluation Module SN65HVD72EVM SN65HVD72EVM 데이터 시트
제품 코드
SN65HVD72EVM
3.3V
PSU1
R
JMP3
1
2
2
VCC
3
4
4
JMP2
1
2
2
VCC
3
4
4
/RE
DE
JMP6
1
2
3
4
2
3
4
B
A
A
1
JMP11
2
3
3
1
2
3
TB1
G
N
D
E
A
R
T
H
V
C
C
HVD7x
EVM1
1
2
3
TB2
Scope
Ch4
Ch3
Ch2
Ch1
B
A
PSU2
Signal
Generator
JMP4
1
2
VCC
3
4
D
JMP3
1
2
VCC
3
4
JMP2
1
2
VCC
3
4
/RE
DE
1
JMP14
2
3
1
2
3
TB1
G
N
D
E
A
R
T
H
V
C
C
HVD7x
EVM2
1
2
3
TB2
B
A
3.3V
3.3V
Powering Up the EVM and Taking Measurements
Figure 8. SN65HVD7xEVM Configurations: Left as Receiver EVM, Right as Transmitter EVM
Figure 9. Top View of SN65HVD7xEVM
7
SLLU162 – March 2012
SN65HVD7xEVM Evaluation Module
Copyright © 2012, Texas Instruments Incorporated