Texas Instruments SN65LVDS4 Evaluation Module SN65LVDS4EVM SN65LVDS4EVM 데이터 시트
제품 코드
SN65LVDS4EVM
Schematic, Bill of Materials, and Board Layouts
6.3
Board Layouts
Table 4. SN65LVDS4EVM Printed-Circuit Board Layer Construction
Subclass
Thickness
Conductivity
Dielectric
Loss
Width
Impedance
Type
Material
Artwork
Name
(mil)
(mho/cm)
Constant
Tangent
(mil)
(
Ω
)
(1)
SURFACE
AIR
MASK
LPI
FINISH
ENIG
1.29
TOP
CONDUCTOR
COPPER
0.689
595900
1
0
POSITIVE
10
50
DIELECTRIC
FR-4
6
0
4.2
0.035
L2_GND
PLANE
COPPER
1.378
595900
1
0
POSITIVE
DIELECTRIC
FR-4
10
0
4.2
0.035
L3_POWER
CONDUCTOR
COPPER
1.378
595900
1
0
POSITIVE
DIELECTRIC
FR-4
6
0
4.2
0.035
BOTTOM
CONDUCTOR
COPPER
0.689
595900
1
0
POSITIVE
N/A
FINISH
ENIG
1.29
MASK
LPI
SURFACE
AIR
(1)
Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance is
achieved.
achieved.
Figure 3. SN65LVDS4EVM Board Layout, Top
–
Layer 1
6
SN65LVDS4 Evaluation Module
SLLU151
–
July 2011
Copyright
©
2011, Texas Instruments Incorporated