Texas Instruments Three Phase BLDC & PMSM Motor Kit with DRV8301 and InstaSPIN-enabled Piccolo TMS320F28069M MCU DRV8301 DRV8301-69M-KIT 데이터 시트

제품 코드

DRV8301-69M-KIT

D0 ACK

Stop

Condition

Acknowledge

I C Device Address and

Read/Write Bit

Subaddress

Last Data Byte

A0 R/W ACK

ACK D7

ACK

Start

Condition

Acknowledge

First Data Byte

Other Data Bytes

ACK

Acknowledge

T0482-01

R/W ACK A7

ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

I C Device Address and

Read/Write Bit

Subaddress

Data Byte

T0481-01

DRV2605

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SLOS825B – DECEMBER 2012 – REVISED JANUARY 2014

SINGLE-BYTE WRITE

As shown in

Figure 20

, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I

C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I

device address and the read/write bit, the DRV2605 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to theDRV2605 internal memory address being accessed. After
receiving the register byte, the DRV2605 again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.

The DRV2605 address is 0x5A (7-bit), or 1011010 in binary.

Figure 20. Single-Byte Write Transfer

MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DRV2605 as shown in

Figure 21

. After receiving each data byte, the

DRV2605 responds with an acknowledge bit.

Figure 21. Multiple-Byte Write Transfer

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