Texas Instruments SRC4392EVM-PDK Evaluation Module SRC4392EVM-PDK SRC4392EVM-PDK 데이터 시트
제품 코드
SRC4392EVM-PDK
X
Channel 1
Y
Channel 2
Channel 1
Z
Y
Channel 2
X
Channel 1
Y
Channel 2
Frame 191
Frame 0
Frame 1
Block Start
One Sub Frame
Bits: 0
3 4
7 8
27 28 29 30 31
MSB
V U C P
Preamble
Audio Data
Audio or
Aux Data
Validity Bit
Use D
r
ata
Channel Status Data
P rit
a y Bit
SBFS029D – DECEMBER 2005 – REVISED DECEMBER 2012
For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and
status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio).
status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio).
shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble,
up to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data
(C), one bit for user data (U), and one bit for setting parity (P).
(C), one bit for user data (U), and one bit for setting parity (P).
The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble
codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in
codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in
. However,
the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the
start of a new block of channel status and user data.
start of a new block of channel status and user data.
Figure 63. AES3 Frame and Subframe Encoding
One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and
user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003
and consumer standards documents. The AES18 standard defines recommended usage and formatting of the
user data bits, while consumer applications may utilize the user data for other purposes. The SRC4392 also
includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for
the channel status and user data assigned to audio Channels 1 and 2. Refer to the
user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003
and consumer standards documents. The AES18 standard defines recommended usage and formatting of the
user data bits, while consumer applications may utilize the user data for other purposes. The SRC4392 also
includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for
the channel status and user data assigned to audio Channels 1 and 2. Refer to the
section for the organization of the buffered channel status and user data for the receiver and
transmitter functions.
The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of
the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data,
then bits 8 through 27 are utilized for audio data, while bits 4 though 7 are utilized for auxiliary data bits.
the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data,
then bits 8 through 27 are utilized for audio data, while bits 4 though 7 are utilized for auxiliary data bits.
The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-
analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0,
then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio
sample is not suitable for conversion or additional processing.
analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is 0,
then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the audio
sample is not suitable for conversion or additional processing.
The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for
even parity. The DIT block in the SRC4392 automatically manages the parity bit, setting it to a 0 or 1 as needed.
The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected.
even parity. The DIT block in the SRC4392 automatically manages the parity bit, setting it to a 0 or 1 as needed.
The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected.
Copyright © 2005–2012, Texas Instruments Incorporated
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