Texas Instruments Evaluation Module for TPS61185 2A WLED Driver IC TPS61185EVM-335 TPS61185EVM-335 데이터 시트
제품 코드
TPS61185EVM-335
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Test Requirements and Setup
5.1.4
J4 – 14-Pin Connector
This header facilitates connecting the TPS61185EVM-335 to the WLEDEVM-260 LED EVM board. This
boards must be ordered separately from the TPS61185.
boards must be ordered separately from the TPS61185.
5.1.5
J5 and J7 – GND
These headers connect to the board's ground plane.
5.1.6
JP1 – LED ON
The user can remove the shunt on this jumper and connect the high side of external LED strings. When
using the WLEDEVM-260 LED EVM, installing the shunt on this jumper connects the output of the boost
converter to J4. Removing the jumper removes the WLEDs from the boost converter feedback path and
causes the integrated circuit's (IC) overvoltage protection circuitry to activate. Instead of the shunt, the
user can place an ammeter across the jumper to measure the total output current (i.e., 8×IFB#).
using the WLEDEVM-260 LED EVM, installing the shunt on this jumper connects the output of the boost
converter to J4. Removing the jumper removes the WLEDs from the boost converter feedback path and
causes the integrated circuit's (IC) overvoltage protection circuitry to activate. Instead of the shunt, the
user can place an ammeter across the jumper to measure the total output current (i.e., 8×IFB#).
5.1.7
JP2 – EN
Installing the shunt on this jumper to ON sets the ENABLE pin voltage to VDD, thereby enabling the IC's
boost converter. Connecting it to OFF pulls EN to ground, which disables the IC's boost converter.
boost converter. Connecting it to OFF pulls EN to ground, which disables the IC's boost converter.
Note: With V
IN
applied, VDD does not reach full regulation until EN is pulled high. While it is possible to
enable the IC by tying the EN pin to the unregulated VDD output for evaluation, it is not recommended
in a real application.
in a real application.
5.1.8
JP3 – PWM
Installing the shunt on this jumper to VDD sets the current sinks to 100% current and therefore any
attached LEDs to full brightness. The user must connect an external PWM signal or use JP3 to take PWM
to a logic high (above 1.2 V but no higher than 6 V) in order to enable the current sinks.
attached LEDs to full brightness. The user must connect an external PWM signal or use JP3 to take PWM
to a logic high (above 1.2 V but no higher than 6 V) in order to enable the current sinks.
5.1.9
JP4 – MODE
Installing the shunt on this jumper connects the MODE pin to GND causing the frequency at which each
current regulator to turn on/off at the same frequency and duty cycle as the input PWM signal on JP3. If
the shunt is not installed, the regulators turn on/off at the same duty cycle as the input PWM signal but at
the frequency programmed by the resistor connected to the FPWM pin (R5).
current regulator to turn on/off at the same frequency and duty cycle as the input PWM signal on JP3. If
the shunt is not installed, the regulators turn on/off at the same duty cycle as the input PWM signal but at
the frequency programmed by the resistor connected to the FPWM pin (R5).
5.1.10
JP5 – JP12
The user can remove the shunt and tie the middle pin of this jumper to an external string of LEDs.
Alternatively, the user can use the shunt to tie the IFBx pin to JPx and then connect JPx to the
WLEDEVM-260 or WLEDEVM-461 boards. For strings that are not used, the user can remove the shunt
entirely or tie the applicable IFBx pin to GND.
Alternatively, the user can use the shunt to tie the IFBx pin to JPx and then connect JPx to the
WLEDEVM-260 or WLEDEVM-461 boards. For strings that are not used, the user can remove the shunt
entirely or tie the applicable IFBx pin to GND.
6
Test Requirements and Setup
6.1
Hardware Requirements
This EVM requires an external power supply capable of providing up to 24 V at 3 A.
If dimming via an external PWM signal is desired, then a function generator capable of providing at least a
2.1-V amplitude PWM signal between 100 Hz to 20 kHz is required to avoid screen flickering and maintain
dimming linearity.
2.1-V amplitude PWM signal between 100 Hz to 20 kHz is required to avoid screen flickering and maintain
dimming linearity.
6.2
Hardware Setup
•
Connect a power supply capable of supplying up to 24 V at 3 A between the VIN pin and GND (J1 and
J3). Do not turn on the power supply.
J3). Do not turn on the power supply.
•
Either set JP2 ON or connect a second logic signal or power supply capable of providing at least 2.1-V
voltage to the high-impedance EN pin of JP2.
voltage to the high-impedance EN pin of JP2.
5
SLVU308 – May 2010
TPS61185EVM-335
Copyright © 2010, Texas Instruments Incorporated