Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 데이터 시트
제품 코드
TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.17.2 SPI Electrical Data/Timing
6.17.2.1 Serial Peripheral Interface (SPI) Timing
through
assume testing over recommended operating conditions (see
through
).
Table 6-64. General Timing Requirements for SPI0 Master Modes
(1)
1.3V, 1.2V
1.1V
1.0V
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
t
c(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
20
(2)
256P
30
(2)
256P
40
(2)
256P
ns
2
t
w(SPCH)M
Pulse Width High, SPI0_CLK, All Master Modes
0.5M-1
0.5M-1
0.5M-1
ns
3
t
w(SPCL)M
Pulse Width Low, SPI0_CLK, All Master Modes
0.5M-1
0.5M-1
0.5M-1
ns
Polarity = 0, Phase = 0,
5
5
6
to SPI0_CLK rising
Polarity = 0, Phase = 1,
-0.5M+5
-0.5M+5
-0.5M+6
Delay, initial data bit valid on
to SPI0_CLK rising
4
t
d(SIMO_SPC)M
SPI0_SIMO after initial edge
ns
Polarity = 1, Phase = 0,
on SPI0_CLK
(3)
5
5
6
to SPI0_CLK falling
Polarity = 1, Phase = 1,
-0.5M+5
-0.5M+5
-0.5M+6
to SPI0_CLK falling
Polarity = 0, Phase = 0,
5
5
6
from SPI0_CLK rising
Polarity = 0, Phase = 1,
5
5
6
Delay, subsequent bits valid
from SPI0_CLK falling
5
t
d(SPC_SIMO)M
on SPI0_SIMO after transmit
ns
Polarity = 1, Phase = 0,
edge of SPI0_CLK
5
5
6
from SPI0_CLK falling
Polarity = 1, Phase = 1,
5
5
6
from SPI0_CLK rising
Polarity = 0, Phase = 0,
0.5M-3
0.5M-3
0.5M-3
from SPI0_CLK falling
Polarity = 0, Phase = 1,
0.5M-3
0.5M-3
0.5M-3
Output hold time, SPI0_SIMO
from SPI0_CLK rising
6
t
oh(SPC_SIMO)M
valid after receive edge of
ns
Polarity = 1, Phase = 0,
SPI0_CLK
0.5M-3
0.5M-3
0.5M-3
from SPI0_CLK rising
Polarity = 1, Phase = 1,
0.5M-3
0.5M-3
0.5M-3
from SPI0_CLK falling
Polarity = 0, Phase = 0,
1.5
1.5
1.5
to SPI0_CLK falling
Polarity = 0, Phase = 1,
1.5
1.5
1.5
Input Setup Time, SPI0_SOMI
to SPI0_CLK rising
7
t
su(SOMI_SPC)M
valid before receive edge of
ns
Polarity = 1, Phase = 0,
SPI0_CLK
1.5
1.5
1.5
to SPI0_CLK rising
Polarity = 1, Phase = 1,
1.5
1.5
1.5
to SPI0_CLK falling
Polarity = 0, Phase = 0,
4
4
5
from SPI0_CLK falling
Polarity = 0, Phase = 1,
4
4
5
Input Hold Time, SPI0_SOMI
from SPI0_CLK rising
8
t
ih(SPC_SOMI)M
valid after receive edge of
ns
Polarity = 1, Phase = 0,
SPI0_CLK
4
4
5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
4
4
5
from SPI0_CLK falling
(1)
P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(2)
This timing is limited by the timing shown or 3P, whichever is greater.
(3)
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
154
Peripheral Information and Electrical Specifications
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