Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 데이터 시트
제품 코드
TMDXEVMWIFI1808L
TCK
TDO
1
7
2
3
RTCK
4
5
6
9
8
TDI/TMS/TRST
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-140. JTAG ID Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:28
VARIANT
Variant (4-Bit) value
27:12
PART NUMBER
Part Number (16-Bit) value
11-1
MANUFACTURER
Manufacturer (11-Bit) value
0
LSB
LSB. This bit is read as a "1".
6.34.4.2
JTAG Test-Port Electrical Data/Timing
Table 6-141. Timing Requirements for JTAG Test Port (see
)
1.3V, 1.2V
1.1V
1.0V
No.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
t
c(TCK)
Cycle time, TCK
40
50
66.6
ns
2
t
w(TCKH)
Pulse duration, TCK high
16
20
26.6
ns
3
t
w(TCKL)
Pulse duration, TCK low
16
20
26.6
ns
4
t
c(RTCK)
Cycle time, RTCK
40
50
66.6
ns
5
t
w(RTCKH)
Pulse duration, RTCK high
16
20
26.6
ns
6
t
w(RTCKL)
Pulse duration, RTCK low
16
20
26.6
ns
7
t
su(TDIV-RTCKH)
Setup time, TDI/TMS/TRST valid before RTCK high
4
4
4
ns
8
t
h(RTCKH-TDIV)
Hold time, TDI/TMS/TRST valid after RTCK high
4
6
8
ns
Table 6-142. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see
)
1.3V, 1.2V
1.1V
1.0V
No.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
9
t
d(RTCKL-TDOV)
Delay time, RTCK low to TDO valid
18
23
31
ns
Figure 6-89. JTAG Test-Port Timing
6.34.5 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
•
Execute a valid reset sequence and exit reset
•
Wait at least 6000 OSCIN clock cycles
•
Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU0 and EMU1 pins for boundary scan testing. If TRST is not driven
by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
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