Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 데이터 시트
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TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-14. EMIFA Supported SDRAM Configurations
(1)
SDRAM
EMIFA Data
Total
Total
Memory
Memory
Number of
Bus Size
Rows
Columns
Banks
Memory
Memory
Density
Data Bus
Memories
(bits)
(Mbits)
(Mbytes)
(Mbits)
Width (bits)
1
16
16
8
1
256
32
256
1
16
16
8
2
512
64
512
1
16
16
8
4
1024
128
1024
1
16
16
9
1
512
64
512
1
16
16
9
2
1024
128
1024
16
1
16
16
9
4
2048
256
2048
1
16
16
10
1
1024
128
1024
1
16
16
10
2
2048
256
2048
1
16
16
10
4
4096
512
4096
1
16
16
11
1
2048
256
2048
1
16
16
11
2
4096
512
4096
1
16
15
11
4
4096
512
4096
2
16
16
8
1
256
32
128
2
16
16
8
2
512
64
256
2
16
16
8
4
1024
128
512
2
16
16
9
1
512
64
256
2
16
16
9
2
1024
128
512
8
2
16
16
9
4
2048
256
1024
2
16
16
10
1
1024
128
512
2
16
16
10
2
2048
256
1024
2
16
16
10
4
4096
512
2048
2
16
16
11
1
2048
256
1024
2
16
16
11
2
4096
512
2048
2
16
15
11
4
4096
512
2048
(1)
The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
supporting these densities are not available in the market.
6.10.3 EMIFA SDRAM Loading Limitations
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
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Peripheral Information and Electrical Specifications
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