Texas Instruments 6A, 3V to 6V Input, SWIFT Converter Evaluation Module TPS54617EVM-414 TPS54617EVM-414 데이터 시트
제품 코드
TPS54617EVM-414
2.9
Powering Up
t − Time − 5 ms/div
V
putV
I
−
In
oltage
−
2V/div
V
putV
O
−
Out
oltage
−
500mV/div
V = 5 V
I
V = 1.8 V
O
0.047 F
Slow-Start Capacitor
Slow-Start Capacitor
m
3
Board Layout
3.1
Layout
Board Layout
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The start-up waveforms are shown in
. The top trace shows V
IN
, and the bottom trace shows
V
OUT
. The top trace shows EN (enable) whereas the bottom trace shows V
OUT
. The input voltage is initially
applied and the output is inhibited by using a jumper at J2 to tie EN to GND. When the jumper is removed,
EN is released. When the EN voltage reaches the enable-threshold voltage of 1.25 V, the start-up
sequence begins and the internal reference voltage begins to ramp up at the internally set rate toward 0.8
V and the output voltage ramps up to the externally set value of 3.3 V. The input voltage for these plots is
15 V and there is no load.
EN is released. When the EN voltage reaches the enable-threshold voltage of 1.25 V, the start-up
sequence begins and the internal reference voltage begins to ramp up at the internally set rate toward 0.8
V and the output voltage ramps up to the externally set value of 3.3 V. The input voltage for these plots is
15 V and there is no load.
Figure 8. TPS54617EVM-414 Start-up Relative to Input Voltage
This section provides a description of the TPS54617EVM-414, board layout, and layer illustrations.
The board layout for the TPS54617EVM-414 is shown in
through
. The topside layer of
the EVM is laid out in a manner typical of a user application. The two internal layers and bottom-side layer
are dedicated ground planes. All layers are 2-oz. copper.
are dedicated ground planes. All layers are 2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54617 and a large area filled with ground. The top, bottom
and internal ground traces are connected with multiple vias placed around the board including twelve vias
directly under the TPS54617 device to provide a thermal path from the top-side ground plane to the
bottom-side ground plane.
and internal ground traces are connected with multiple vias placed around the board including twelve vias
directly under the TPS54617 device to provide a thermal path from the top-side ground plane to the
bottom-side ground plane.
The input decoupling capacitors (C1, C2, and C12) and bootstrap capacitor (C6) are all located as close to
the IC as possible. In addition, the voltage set-point resistor divider and compensation components are
also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation,
the V
the IC as possible. In addition, the voltage set-point resistor divider and compensation components are
also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation,
the V
OUT
copper pour areanear the output connector J2 and TP1. For the TPS54617, an additional input
bulk capacitor C13 may be required, depending on the EVM connection to the input supply.
8
TPS54617EVM-414 6-A, SWIFT™ Regulator Evaluation Module
SLVU279 – December 2008