Texas Instruments TPA3130D2 Evaluation Module TPA3130D2EVM TPA3130D2EVM 데이터 시트
제품 코드
TPA3130D2EVM
+
–
+
–
+
–
+
+
SDZ
MUTE
TTL
Buffer
Gain
Control
GAIN
OUTPR_FB
RINP
RINN
Gain
Control
OUTPNR_FB
FAULTZ
SYNC
GAIN/SLV
AM<2:0>
PLIMIT
AVCC
GVDD
LDO
Regulator
LINP
LINN
GND
Input
Sense
PBTL
Select
OUTPL_FB
Gain
Control
OUTNL_FB
AVDD
GVDD
PLIMIT
Reference
Ramp
Generator
Biases and
References
Startup Protection
Logic
SC Detect
DC Detect
Thermal
Detect
UVLO/OVLO
PVCC
GVDD
PVCC
Gate
Drive
OUTNL_
FB
PVCC
GVDD
PVCC
Gate
Drive
PWM
Logic
Logic
Modulation and
PBTL Select
OUTPL_FB
GND
OUTPL
BSPL
GND
OUTNL
BSNL
GND
BSNR
OUTPR
GND
OUTNR
OUTNR_
FB
BSPR
OUTPR_FB
PVCC
GVDD
PVCC
Gate
Drive
PVCC
GVDD
PVCC
Gate
Drive
PWM
Logic
Logic
Modulation and
PBTL Select
PLIMIT
PLIMIT
+
–
+
–
+
–
+
–
+
–
+
–
–
–
Thermal
Pad
+
–
PVCC
PVCC
SLOS708C – APRIL 2012 – REVISED NOVEMBER 2013
SYSTEM BLOCK DIAGRAM
4
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: