Texas Instruments Evaluation Module for TPS2480 Positive Voltage Hotswap Controller and I2C Current Monitor TPS2480EVM-0 TPS2480EVM-002 데이터 시트
제품 코드
TPS2480EVM-002
EVM Assembly Drawing and Layout Guidelines
Figure 11. Bottom Side Placement/Routing
6.2
Layout Guidelines
The TPS2480/1 circuit layout must follow power and EMI/ESD best-practice guidelines. A basic set of
recommendations include:
recommendations include:
•
Arrange the high-power devices so that current flows in a sequential, linear fashion.
•
Place a good ground plane under the power planes and TPS2480/1.
•
The TPS2480/81 must be placed close to the sense resistor and MOSFET using a Kelvin type
connection to achieve accurate current sensing.
connection to achieve accurate current sensing.
•
A low-impedance GND connection is required because the TPS2480/81 can momentarily sink upwards
of 100 mA from the gate of the MOSFET. The GATE amplifier has high bandwidth while active, so
keep the GATE trace length short.
of 100 mA from the gate of the MOSFET. The GATE amplifier has high bandwidth while active, so
keep the GATE trace length short.
•
Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input
voltage rails and between the input and an isolated converter output.
voltage rails and between the input and an isolated converter output.
•
Large copper fills and traces must be used on SMT power-dissipating devices, and wide traces or
overlay copper fills must be used in the power path.
overlay copper fills must be used in the power path.
•
The PROG, TIMER, and EN pins have high input impedances; therefore, their input lead length must
be minimized.
be minimized.
•
Oversize power traces and power device connections assuring low voltage drop and good thermal
performance.
performance.
12
TPS2480 and TPS2481 Evaluation Module
SLUU370A – January 2010 – Revised June 2010
Copyright © 2010, Texas Instruments Incorporated