Texas Instruments Evaluation Module for TPS720105 TPS720105DRVEVM TPS720105DRVEVM 데이터 시트
제품 코드
TPS720105DRVEVM
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS720xx
SBVS100D – JUNE 2008 – REVISED AUGUST 2009
........................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT
V
OUT
(2)
TPS720xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V).
YYY is the package designator.
Z is tape and reel quantity (R = 3000, T = 250).
YYY is the package designator.
Z is tape and reel quantity (R = 3000, T = 250).
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at
website at
(2)
Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
minimum order quantities may apply. Contact factory for details and availability.
At T
J
= –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS720xx
UNIT
Input voltage range (steady-state), V
IN
(2)
–0.3 to V
BIAS
or +5.0
(3)
V
Peak transient input voltage, V
IN_PEAK
(4)
+5.5
V
Bias voltage range, V
BIAS
–0.3 to +6.0
V
Enable voltage range, V
EN
–0.3 to +6.0
V
Output voltage range, V
OUT
–0.3 to +5.0
V
Peak output current, I
OUT
Internally limited
Output short-circuit duration
Indefinite
Total continuous power dissipation, P
DISS
See
Table
Human body model (HBM)
2000
V
ESD rating
Charged device model (CDM)
500
V
Machine model (MM)
100
V
Operating junction temperature range, T
J
–55 to +125
°C
Storage temperature range, T
STG
–55 to +150
°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2)
To ensure proper operation of the device it is necessary that V
IN
≤ V
BIAS
under all conditions.
(3)
Whichever is less.
(4)
For durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device.
DERATING FACTOR
BOARD
PACKAGE
R
θ
JC
R
θ
JA
ABOVE T
A
= +25°C
T
A
< +25°C
T
A
= +70°C
T
A
= +85°C
High-K
(1)
YZU
51°C/W
248°C/W
4mW/°C
403mW
222mW
160mW
High-K
(1)
DRV
20°C/W
65°C/W
15.4mW/°C
1580mW
845mW
615mW
(1)
The JEDEC high-K (2s2p) board used to derive this data was a 3- × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
planes and 2-ounce copper traces on top and bottom of the board.
2
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