Texas Instruments DS100KR800EVK evaluation board DS100KR800EVK/NOPB DS100KR800EVK/NOPB 데이터 시트
제품 코드
DS100KR800EVK/NOPB
SNLS340D – NOVEMBER 2011 – REVISED APRIL 2013
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS100KR800 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V
DD
and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1
bypassing through the proper use of bypass capacitors is required. A 0.1
μ
F bypass capacitor should be
connected to each V
DD
pin such that the capacitor is placed as close as possible to the DS100KR800. Smaller
body size capacitors can help facilitate proper component placement. In the case of 3.3V mode operation with
the internal LDO regulator, recommend using capacitors with capacitance in the range of 1.0
the internal LDO regulator, recommend using capacitors with capacitance in the range of 1.0
μ
F to 10
μ
F should
be incorporated in the power supply bypassing design for the VIN pin. These capacitors should be ultra-low ESR
ceramic.
ceramic.
Copyright © 2011–2013, Texas Instruments Incorporated
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