Texas Instruments 3.3Vout, 10W, IEEE 802.3-2005 Compliant PD Controller, PS Controller Evaluation Module for TPS23753A T TPS23753AEVM-004 데이터 시트
제품 코드
TPS23753AEVM-004
(
)
(
)
BLNK
BLNK
R
k
t
ns
Ω =
_
_
(
)
(
)
( )
1000
(
)
SLOPE
SLOPE
D
MAX
S
SL
EX
V
mV
V
mV
D
R
I
A
µ
−
Ω =
⋅
TPS23753A
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SLVS933B – JULY 2009 – REVISED JANUARY 2010
Special Switching MOSFET Considerations
Special care must be used in selecting the converter switching MOSFET. The TPS23753A converter section has
minimum V
minimum V
C
operating voltage of ~5.5 V, which is reflected in the applied gate voltage. This will occur during an
output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the
anticipated peak fault current at this gate voltage.
anticipated peak fault current at this gate voltage.
Thermal Considerations
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23753A is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23753A device to experience an OTSD event if it is excessively heated by a nearby
device.
assume that the TPS23753A is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23753A device to experience an OTSD event if it is excessively heated by a nearby
device.
Blanking – R
BLNK
The TPS23753A BLNK feature permits programming of the blanking period with specified tolerance. Selection of
the blanking period is often empirical because it is affected by parasitics and thermal effects of every device
between the gate-driver and output capacitors.
the blanking period is often empirical because it is affected by parasitics and thermal effects of every device
between the gate-driver and output capacitors.
There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long
side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum
blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent
current “spike” that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by
the output rectifier's ability to withstand the currents experienced during a converter output short.
side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum
blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent
current “spike” that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by
the output rectifier's ability to withstand the currents experienced during a converter output short.
The TPS23753A provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with a resistor from BLNK to RTN per the following equation.
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with a resistor from BLNK to RTN per the following equation.
(5)
For example, a 100 ns period is programmed by a 100 k
Ω
resistor. For a brand-new design, it is recommended
that an initial blanking period of 125 ns be designed in. This period should be tuned once the converter is
operational.
operational.
Current Slope Compensation
Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)
current for stability at duty cycles near and over 50%. The TPS23753A has a maximum duty cycle limit of 78%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a
narrower, 36 V to 57 V range. The TPS23753A provides a fixed internal compensation ramp that suffices for
most applications. R
current for stability at duty cycles near and over 50%. The TPS23753A has a maximum duty cycle limit of 78%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a
narrower, 36 V to 57 V range. The TPS23753A provides a fixed internal compensation ramp that suffices for
most applications. R
S
(see
) may be used if the internally provided slope compensation is not enough. It
works with ramp current (I
PK
= I
SL-EX
, ~40
m
A) that flows out of the CS pin when the MOSFET is on. The I
PK
specification does not include the ~3
m
A fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of V
PP
/T
S
(peak ramp
voltage / switching period), however the electrical characteristics table specifies the slope peak (V
SLOPE
) based
on the maximum duty cycle. Assuming that the desired slope, V
SLOPE-D
(in mV/period), is based on the full period,
compute R
S
per the following equation where V
SLOPE
, D
MAX
, and I
SL-EX
are from the electrical characteristics table
with voltages in mV, current in
m
A, and the duty cycle is unitless (e.g. D
MAX
= 0.78).
(6)
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