Texas Instruments SEPIC Evaluation Module for TPS55340 TPS55340EVM-147 TPS55340EVM-147 데이터 시트
제품 코드
TPS55340EVM-147
C3: V
IN
(2.00 V/div)
C2: V
OUT
(5.00 V/div)
C1: SW (10.0 V/div)
Timebase = 5.00 ms/div
Board Layout
shows the shutdown waveforms for the TPS55340EVM-147. The input voltage ramps down with
the input voltage power supply and EN is tied to V
IN
. When V
IN
is less than the 2.6V typical UVLO, the
converter stops switching and the output voltage ramps down. The load is 120
Ω.
Figure 16. TPS55340EVM-147 Power Down With V
IN
5
Board Layout
This section provides a description of the TPS55340EVM-147 board layout and layer illustrations.
5.1
Layout
The board layout for the TPS55340EVM-147 is shown in
through
. The top-side layer
of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-
oz. copper.
oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and SW. Also on the top layer are connections
for the remaining pins of the TPS55340 and a large area filled with ground. The internal layers and bottom
are primarily ground with additional fill areas for V
are primarily ground with additional fill areas for V
IN
, and V
OUT
. The top-side ground traces connect to the
bottom and internal ground planes with multiple vias placed around the board. Nine vias directly under the
TPS55340 device provide a thermal path from the top-side ground plane to the bottom-side ground plane.
TPS55340 device provide a thermal path from the top-side ground plane to the bottom-side ground plane.
Place the output decoupling capacitors (C8-C11) as close to the IC as possible. The copper area of the
SW node is kept small to minimize noise. The vias near the diode D1 on the V
SW node is kept small to minimize noise. The vias near the diode D1 on the V
OUT
plane aid with thermal
dissipation. Additionally, keep the voltage setpoint resistor divider components close to the IC. The voltage
divider network ties to the output voltage at the point of regulation, the copper V
divider network ties to the output voltage at the point of regulation, the copper V
OUT
trace at the J7 output
connector. For the TPS55340, an additional input bulk capacitor may be necessary, depending on the
EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency
set resistor, slow-start capacitor, and compensation components terminate to ground by using a separate
ground trace on the top and bottom connected power ground pour only at one point directly under the IC.
EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency
set resistor, slow-start capacitor, and compensation components terminate to ground by using a separate
ground trace on the top and bottom connected power ground pour only at one point directly under the IC.
12
TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module
SLVU742A – June 2012 – Revised August 2013
Copyright © 2012–2013, Texas Instruments Incorporated