Texas Instruments IC MCU 16B MSP430F167IPM LQFP-64 TID MSP430F167IPM 데이터 시트

MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER

SLAS368G − OCTOBER 2002 − REVISED MARCH 2011

40

POST OFFICE BOX 655303 

•

 DALLAS, TEXAS 75265

V

Positive built-in reference

REF2_5V = 1 for 2.5 V
I

VREF+

max

≤

I

VREF+

≤

I

VREF+

min

V

CC

 = 3 V

2.4

2.5

2.6

V

V

REF+

Positive built in reference
voltage output

REF2_5V = 0 for 1.5 V
I

VREF+

max

≤

I

VREF+

≤

I

VREF+

min

V

CC

 = 2.2 V/3 V

1.44

1.5

1.56

V

AV

CC

minimum voltage,

REF2_5V = 0, I

VREF+

max

≤

I

VREF+

≤

I

VREF+

min

2.2

AV

CC(min)

AV

CC

 minimum voltage,

Positive built-in reference

REF2_5V = 1, −0.5mA 

≤

I

VREF+

≤

I

VREF+

min

2.8

V

AV

CC(min)

Positive built in reference
active

REF2_5V = 1, −1mA 

≤

I

VREF+

≤

I

VREF+

min

2.9

V

I

Load current out of V

REF+

V

CC

 = 2.2 V

0.01

−0.5

mA

I

VREF+

Load current out of V

REF+

terminal

V

CC

 = 3 V

0.01

−1

mA

I

VREF+ 

= 500 

μ

A +/− 100 

μ

A

Analog input voltage 0 75 V

V

CC

 = 2.2 V

±

2

LSB

I

†

Load-current regulation

Analog input voltage ~0.75 V, 
REF2_5V = 0

V

CC

 = 3 V

±

2

LSB

I

L(VREF)+ 

†

Load current regulation
V

REF+ 

terminal

I

VREF+ 

= 500 

μ

A 

±

 100 

μ

A

Analog input voltage ~1.25 V,
REF2_5V = 1

V

CC

 = 3 V

±

2

LSB

I

‡

Load current regulation

I

VREF+ 

=100 

μ

A 

→

 900 

μ

A,

C

5

μ

F ax 0 5 x V

V

3 V

20

ns

I

DL(VREF) +

‡

Load current regulation
V

REF+ 

terminal

C

VREF+

=5 

μ

F, ax ~0.5 x V

REF+

 ,

Error of conversion result 

≤

 1 LSB

V

CC

 = 3 V

20

ns

C

VREF+

Capacitance at pin V

REF+

(see Note 1)

REFON =1, 
0 mA 

≤

 I

VREF+

≤

I

VREF+

max

V

CC

 = 2.2 V/3 V

5

10

μ

F

T

REF+

†

Temperature coefficient of
built-in reference

I

VREF+ 

is a constant in the range of

0 mA 

≤

 I

VREF+

 

≤

 1 mA

V

CC

 = 2.2 V/3 V

±

100

ppm/

°

C

t

REFON

†

Settle time of internal
reference voltage (see
Figure 16 and Note 2)

I

VREF+ 

= 0.5 mA, C

VREF+

 = 10 

μ

F, V

REF+ 

= 1.5 V,

V

AVCC

 = 2.2 V

17

ms

†

Not production tested, limits characterized

‡

Not production tested, limits verified by design

NOTES:

1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses

two capacitors between pins V

REF+

 and AV

SS

 and V

REF−

/V

eREF−

 and AV

SS

: 10 

μ

F tantalum and 100 nF ceramic.

2. The condition is that the error in a conversion started after t

REFON

 is less than 

±

0.5 LSB. The settling time depends on the external

capacitive load.

 μ

≈

μ

 μ

 μ