Texas Instruments IC MCU 16B MSP430F167IPM LQFP-64 TID MSP430F167IPM 데이터 시트
제품 코드
MSP430F167IPM
MSP430F15x, MSP430F16x, MSP430F161x
MIXED SIGNAL MICROCONTROLLER
MIXED SIGNAL MICROCONTROLLER
SLAS368G − OCTOBER 2002 − REVISED MARCH 2011
56
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics (continued)
port P3, P3.2, input/output with Schmitt trigger
P3.2/SOMI0
P3IN.2
Pad Logic
EN
D
P3OUT.2
P3DIR.2
P3SEL.2
0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)0
From USART0
(SO)MI0
To USART0
0: Input
1: Output
1: Output
port P3, P3.3, input/output with Schmitt-trigger
P3.3/UCLK0/SCL
P3IN.3
Pad Logic
EN
D
P3OUT.3
P3DIR.3
P3SEL.3
UCLK.0
0
1
0
1
DCM_UCLK
SYNC
MM
STE
STC
From USART0
UCLK0
To USART0
0: Input
1: Output
1: Output
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode:
The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
I
2
C, slave mode:
The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be
w
10 times the frequency of the SCL clock.
I
2
C, master mode:
To shift data in and out, the clock is supplied via the SCL terminal to all I
2
C slaves. The frequency of the clock source
of the module must be
w
10 times the frequency of the SCL clock.