Texas Instruments PCM5142 Evaluation Module PCM5142EVM-U PCM5142EVM-U 데이터 시트
제품 코드
PCM5142EVM-U
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
Audio Data Interface
Audio Serial Interface
The audio interface port is a 3-wire serial port with the signals LRCK (pin 15), BCK (pin 13), and DIN (pin 14).
BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the
audio interface. Serial data is clocked into the PCM514x on the rising edge of BCK. LRCK is the serial audio
left/right word clock.
BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the
audio interface. Serial data is clocked into the PCM514x on the rising edge of BCK. LRCK is the serial audio
left/right word clock.
Table 15. PCM514x Audio Data Formats, Bit Depths and Clock Rates
MAX LRCK
CONTROL MODE
FORMAT
DATA BITS
SCK RATE [x f
S
]
BCK RATE [x f
S
]
FREQUENCY [f
S
]
Up to 192kHz
128 – 3072
64, 48, 32
I
2
S/LJ
32, 24, 20, 16
384kHz
64, 128
64, 48, 32
Software Control
Up to 48kHz
128 – 3072
125, 256
(SPI or I
2
S)
TDM
32, 24, 20, 16
96kHz
128 – 512
125, 256
192kHz
128, 192, 256
128
Up to 192kHz
128 – 3072
64, 48, 32
Hardware Control
I
2
S/LJ
32, 24, 20, 16
384kHz
64, 128
64, 48, 32
The PCM514x requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
Copyright © 2012, Texas Instruments Incorporated
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