Texas Instruments DP130 Dual-Source Evaluation Module DP130DSEVM DP130DSEVM 데이터 시트
제품 코드
DP130DSEVM
VCC
0 V
VCC
0 V
tPD(HPD)
HPD_SNK
HPD_SRC
50%
50%
V
CC
0 V
V
OH
VOL
HPD_SRC
HPD_SNK
Sink Hot Plug
Detect Timeout
t
T(HPD)
50%
50%
Device active
Low power
HPD_SRC
SN75DP130
TP
TP
HPD_SNK
100 KW
130 KW
SLLSE57D – APRIL 2011 – REVISED JULY 2013
Figure 10. HPD Test Circuit
Figure 11. HPD Timing Diagram 1
Figure 12. HPD Timing Diagram 2
AUX/DDC/I
2
C ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
PASS
DDC mode passthrough voltage
V
CAD_SNK
= V
IH
; I
O
= 100 µA
1.9
V
C
IO
I/O capacitance
V
IO
= 0 V; f(test) = 1 MHz
10
pF
On resistance AUX_SRCn to AUX_SNKn in DP
V
CC
= 3.0 V w/ V
I
=2.85V or
5
10
Ω
mode
V
CC
= 3.6 V w/ V
I
= 3.4 V; I
O
= 5 mA
On resistance SCL/SDA_DDC to AUX_SNK in
r
ON
I
O
= 3 mA
15
30
Ω
TMDS mode
On resistance AUX_SRC to AUX_SNK in TMDS
I
O
= 3 mA
10
20
Ω
mode
On resistance variation with input signal voltage
V
CC
= 3.6 V, I
O
= 5 mA, V
I
= 2.6 to 3.4 V,
Δr
ON
5
Ω
change in DP mode
V
CC
= 3.0 V, I
O
= 5 mA, V
I
= 0 to 0.4 V
V
ID(HYS)
Differential input hysterisis
By design (simulation only)
50
mV
I
H
High-level input current
V
I
= V
CC
-5
5
µA
V
I
= GND; CAD_SNK = V
IH
-5
5
I
L
Low-level input current
µA
V
I
= GND; At DDC inputs
80
1M (5%) pullup to V
CC
and 100k
Ω pulldown to GND on
V
AUX+
Voltage on the Aux+ for PHY-CTS 3.19
0
0.4
V
AUX+; V
CC
= 3.3 V
100k
Ω pullup to V
CC
and 1M (5%) pulldown to GND on
V
AUX-
Voltage on the Aux- for PHY-CTS 3.18
AUX-;
2.4
3.6
V
V
CC
= 3.3 V
V
ID
= 400 mV, AC coupled; p-channel biasing 0.3 V and
|S
1122
|
Differential line insertion loss
1.6
3
dB
n-channel 3.0V; 360 MHz sine wave; CAD_SNK=V
IL
Switcheable pul-lup resistor on DDC at source
R
DDC
CAD_SNK = V
IH
48
60
72
k
Ω
side (SCL_DDC, SDA_DDC)
Copyright © 2011–2013, Texas Instruments Incorporated
15
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