Texas Instruments Evaluation Module for TPS54427 TPS54427EVM-052 TPS54427EVM-052 데이터 시트
제품 코드
TPS54427EVM-052
V
500 mV/div
OUT
Time 0.5 ms/div
I
200 mA/div
IN
EN 2 V/div
VREG5 2 V/div
V
500 mV/div
OUT
I
500 mA/div
IN
EN 2 V/div
VREG5 2 V/div
Time 0.5 s/div
Board Layout
The TPS54427 start-up and shut-down waveforms relative to enable (EN) are shown in
and
Figure 10. TPS54427 Start-Up Relative to EN
Figure 11. TPS54427 Shut-down Relative to EN
5
Board Layout
This section provides description of the TPS54427, board layout, and layer illustrations.
5.1
Layout
The board layout for the TPS54427 is shown in
through
. The top layer contains the
main power traces for V
IN
, V
OUT
, and ground. Also on the top layer are connections for the pins of the
TPS54427 and a large area filled with ground. Many of the signal traces also are located on the top side.
The input decoupling capacitors are located as close to the IC as possible. The input and output
connectors, test points, and all of the components are located on the top side. An analog ground (GND)
area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a
single point on the top layer near C6. The bottom layer is primarily power ground but also has a trace to
connect V
The input decoupling capacitors are located as close to the IC as possible. The input and output
connectors, test points, and all of the components are located on the top side. An analog ground (GND)
area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a
single point on the top layer near C6. The bottom layer is primarily power ground but also has a trace to
connect V
IN
to the enable jumper, a trace to connect VREG5 to TP5, and the feedback trace from V
OUT
to
the voltage setpoint divider network.
Figure 12. Top Assembly
9
SLVU579
–
December 2011
TPS54427, 4-A, SWIFT
™
Regulator
—
Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated