Texas Instruments FPD Link III - DS90UB901Q & DS90UB902Q EVK SERDESUB-16USB/NOPB SERDESUB-16USB/NOPB 데이터 시트

 

20 

SNLU100 – April 2012 

 

 
This section describes how to perform I2C instructions between MCU/FPGA and a remote 
peripheral device through the DS90UB902Q and DS90UB901Q pair configured in a 
camera type of application. Figure 4 shows the configuration of evaluation boards for I2C 
communication. A MCU/FPGA controller with an I2C interface is required. Refer to the 
DS90UB901Q/902Q datasheet for the definition of each register.  
 
 
 
 

SCL

SD
A

VDD18

VDDI

O

VDD18

VDDI

O

 

 

 
 

 
In Camera mode, I2C transactions originate from the Master controller at the Deserializer 
side (Figure 4). The I2C slave core in the Deserializer will detect if a transaction is 
intended for the Serializer or a slave at the Serializer. Commands are sent over the bi-
directional control channel to initiate the transactions. The Serializer will receive the 
command and generate an I2C transaction on its local I2C bus. At the same time, the 
Serializer will capture the response on the I2C bus and return the response on the forward 
channel link. The Deserializer parses the response and passes the appropriate response 
to the Deserializer I2C bus.