Microchip Technology DM300023 데이터 시트

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dsPIC30F1010/202X
DS80000391B-page 14
 2008-2013 Microchip Technology Inc.
32. Module: CPU
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. 
 shows how the application
should process the Carry bit during a BCD addition
operation.
Affected Silicon Revisions
EXAMPLE 2:
CHECK CARRY BIT BEFORE 
DAW.b
33. Module: PWM
In Push-Pull mode, with immediate updates
enabled, the PWM pins may become swapped.
Work around
If using the PWM module in Push-Pull mode,
immediate updates must be disabled. 
Affected Silicon Revisions
34. Module: PWM
The Dead-Time registers (DTRx/ALTDTRx) must
be modified only when the PWM is not running.
Adjusting the dead time “on-the-fly” can result in
an unpredictable glitch on the PWM output, which
may cause shoot-through.
Work around
None. 
Affected Silicon Revisions
35. Module: UART
When the UART is configured for IR interface
operations (U1MODE<9:8> = 11), the 16x baud
rate clock signal on the BCLK pin is present only
when the module is transmitting. The pin is Idle at
all other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or is in an Idle state.
Affected Silicon Revisions
36. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one. 
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
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.include “p30fxxxx.inc”
.......
mov.b
#0x80, w0
;First BCD number
mov.b
#0x80, w1
;Second BCD number
add.b
w0, w1, w2 ;Perform addition
bra
NC, L0
;If C set go to L0
daw.b
w2
;If not, do DAW and
bset.b SR, #C
;set the carry bit
bra
L1
;and exit
L0:daw.b
w2
L1: ....
A0
A1
A2
A3
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A0
A1
A2
A3
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A0
A1
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