Microchip Technology DM300023 데이터 시트

© 2008 Microchip Technology Inc.

DS80391A-page 5

The power supply PWM module has a feature to
enable immediate duty cycle updates. This feature
is enabled by setting IUE = 1 in the PWMCONx
register. The dsPIC30F1010/202X device data
sheet states that the minimum PWM duty cycle
value is 0x0010. Duty cycle values less than
0x0010 should cause the PWM outputs to display
states corresponding to a duty cycle value of
0x0000. 

When the immediate duty cycle updates are
enabled, and a value of 0x0010 or less is loaded
into the selected duty cycle register, the outputs of
the PWM generator (PWMxH and PWMxL) will
exhibit a state opposite to the expected state. For
example, if the expected state of the PWM output
is a continuous ‘0’, then a continuous ‘1’ will be
observed, and vice versa.

The above behavior applies when the Master Duty
Cycle (MDC) register or Individual Duty Cycle
(PDCx) register provides the duty cycle value.

If immediate duty cycle updates are enabled, do
not load the duty cycle register with a value less
than or equal to 0x0010. If immediate duty cycle
updates are not enabled, no action is required
because the correct PWM state will be exhibited
for all duty cycle values.

The “dsPIC30F1010/202X Data Sheet”
(DS70178) states the priority of PWMx pin
ownership as:

• PWM Generator (lowest priority)

• Output Override

• Current-Limit Override

• Fault Override

• PENx (GPIO/PWM) Ownership (highest 

priority)

Instead of following the above priority scheme, the
PWMx pin ownership is determined by ANDing the
Output Override Data bits (OVRDAT<1:0>),
Current-Limit Override Data bits (CLDAT<1:0>)
and Fault Override Data bits (FLTDAT<1:0>) in the
IOCONx register.

For example, the override data may be set as
follows:

• OVRDAT<1:0> = 00

• CLDAT<1:0> = 01

• FLTDAT<1:0> = 10

If all three overrides occur simultaneously, the
following operations shown in Equation 1 will
determine the state of the PWMx pin.

Therefore, when multiple overrides occur
simultaneously, only the override data for the
active override sources will be ANDed together
while the inactive override sources will be ignored. 

If only one override is active, override priorities do
not apply and operation of the PWM overrides is
normal.

None.