Texas Instruments ADC12C105 Evaluation Board ADC12C105EB/NOPB ADC12C105EB/NOPB 데이터 시트
제품 코드
ADC12C105EB/NOPB
SNAS417B – MAY 2007 – REVISED AUGUST 2007
ADC12C105 12-Bit, 95/105 MSPS A/D Converter
Check for Samples:
1
FEATURES
DESCRIPTION
The ADC12C105 is a high-performance CMOS
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•
1 GHz Full Power Bandwidth
analog-to-digital
converter
capable
of
converting
•
Internal Reference and Sample-and-Hold
analog input signals into 12-bit digital words at rates
Circuit
up to 105 Mega Samples Per Second (MSPS). This
•
Low Power Consumption
converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-
with digital error correction and an on-chip sample-
•
Data Ready Output Clock
and-hold circuit to minimize power consumption and
•
Clock Duty Cycle Stabilizer
the
external
component
count,
while
providing
•
Single +3.0V or +3.3V Supply Operation
excellent dynamic performance. A unique sample-
and-hold stage yields a full-power bandwidth of 1
and-hold stage yields a full-power bandwidth of 1
•
Power-Down Mode
GHz. The ADC12C105 may be operated from a
•
32-Pin WQFN Package, (5x5x0.8mm, 0.5mm
single +3.0V or +3.3V power supply and consumes
Pin-Pitch)
low power.
A separate +2.5V supply may be used for the digital
APPLICATIONS
output interface which allows lower power operation
•
High IF Sampling Receivers
with reduced noise. A power-down feature reduces
the power consumption to very low levels while still
the power consumption to very low levels while still
•
Wireless Base Station Receivers
allowing fast wake-up time to full operation. The
•
Test and Measurement Equipment
differential inputs accept a 2V full scale differential
•
Communications Instrumentation
input swing. A stable 1.2V internal voltage reference
•
Portable Instrumentation
is provided, or the ADC12C105 can be operated with
an external 1.2V reference. Output data format (offset
binary versus 2's complement) and duty cycle
an external 1.2V reference. Output data format (offset
binary versus 2's complement) and duty cycle
KEY SPECIFICATIONS
stabilizer are pin-selectable. The duty cycle stabilizer
•
Resolution 12 Bits
maintains performance over a wide range of clock
•
Conversion Rate 105 MSPS
duty cycles.
•
SNR (f
IN
= 240 MHz) 69 dBFS (typ)
The ADC12C105 is available in a 32-lead WQFN
•
SFDR (f
IN
= 240 MHz) 82 dBFS (typ)
package and operates over the industrial temperature
range of
range of
−
40°C to +85°C.
•
Full Power Bandwidth 1 GHz (typ)
•
Power Consumption
–
350 mW (typ), V
A
=3.0 V
–
400 mW (typ), V
A
=3.3 V
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.