Texas Instruments DAC8832EVM-PDK - DAC8832 Performance Demonstration Kit DAC8832EVM-PDK DAC8832EVM-PDK 데이터 시트
제품 코드
DAC8832EVM-PDK
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Using the DAC8832EVM with DXP
4.4
DAC Output Update Options
The DXP software also allows the user to choose several DAC output update options, as
shows.
Figure 12. DAC Output Update Options
lists the details of these options.
Table 6. Output Update Features
Options
Detailed Description
Frame Sync
The DXP software defaults to Frame Sync. The Frame Sync output of the MMB0
connects to the CS input of the DAC8832. In this mode, the LDAC pin is held low and
the DAC latch is transparent. The DAC output changes to the corresponding level
simultaneously when the DAC latch is updated via SDI. Place a shunt jumper on W3
covering pins 1-2 (default) to use this option.
connects to the CS input of the DAC8832. In this mode, the LDAC pin is held low and
the DAC latch is transparent. The DAC output changes to the corresponding level
simultaneously when the DAC latch is updated via SDI. Place a shunt jumper on W3
covering pins 1-2 (default) to use this option.
Latch with DSP Timer
Jumper W3 on the EVM controls LDAC selection. In this configuration, a timer function
on the MMB0 applies a pulse to the LDAC pin and the output of the DAC8832 is
updated synchronously with the falling edge of the applied pulse. Place the shunt
jumper on W3 pins 2-3 to use this feature.
on the MMB0 applies a pulse to the LDAC pin and the output of the DAC8832 is
updated synchronously with the falling edge of the applied pulse. Place the shunt
jumper on W3 pins 2-3 to use this feature.
Latch with External Timer
N/A
Update Rate
User Input - enter the desired DAC update rate; 1MSPS is the default
17
SLAU202A – December 2006 – Revised November 2009
DAC8831/32 Evaluation Module
Copyright © 2006–2009, Texas Instruments Incorporated