Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 데이터 시트
제품 코드
DM240013-2
2013 Microchip Technology Inc.
DS30003030B-page 167
PIC24FV16KM204 FAMILY
REGISTER 14-5:
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
2
C™ MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
)
ACKEN
(
)
RCEN
PEN
(
)
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented:
Read as ‘0’
bit 7
GCEN:
General Call Enable bit (Slave mode only)
1
= Enables interrupt when a general call address (0000h) is received in the SSPxSR
0
= General call address is disabled
bit 6
ACKSTAT:
Acknowledge Status bit (Master Transmit mode only)
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
bit 5
ACKDT:
Acknowledge Data bit (Master Receive mode only)
(
)
1
= No Acknowledge
0
= Acknowledge
bit 4
ACKEN:
Acknowledge Sequence Enable bit (Master mode only)
(
)
1
= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
automatically cleared by hardware
0
= Acknowledge sequence is Idle
bit 3
RCEN:
Receive Enable bit (Master Receive mode only)
1
= Enables Receive mode for I
2
C
0
= Receive is Idle
bit 2
PEN:
Stop Condition Enable bit (Master mode only)
(
)
1
= Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0
= Stop condition is Idle
bit 1
RSEN:
Repeated Start Condition Enable bit (Master mode only)
(
)
1
= Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0
= Repeated Start condition is Idle
bit 0
SEN:
Start Condition Enable bit
(
)
Master Mode:
1
= Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0
= Start condition is Idle
Slave Mode:
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch is enabled)
0
= Clock stretching is disabled
Note 1:
The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
receive.
2:
If the I
2
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).