Microchip Technology MA330028 데이터 시트
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533H-page 10
2011-2014 Microchip Technology Inc.
11. Module: PWM
When dead-time compensation is enabled
(DTC<1:0> (PWMCONx<7:6>) = 11) in
Center-Aligned mode (CAM (PWMCONx<2>) = 1),
the dead time, as specified in the ALTDTRx
register, is not being applied to the PWMxH output.
The leading and trailing edges of the PWMxL
output are extended by one-half the value of the
ALTDTRx register, but the PWMxH leading and
trailing edges are unaffected.
(DTC<1:0> (PWMCONx<7:6>) = 11) in
Center-Aligned mode (CAM (PWMCONx<2>) = 1),
the dead time, as specified in the ALTDTRx
register, is not being applied to the PWMxH output.
The leading and trailing edges of the PWMxL
output are extended by one-half the value of the
ALTDTRx register, but the PWMxH leading and
trailing edges are unaffected.
Work around
Using the values from the “dsPIC33E/PIC24E
Family Reference Manual”,
Family Reference Manual”,
Section 14.
“High-Speed PWM” (DS70645), adjust the PWM
parameters as follows:
parameters as follows:
• Subtract one-half of the ALTDTR dead time
from PDCx
• Use twice the value for ALTDTR. For example:
- Frequency of 60 kHz, duty cycle of 50%
- Desired dead time of 833 ns and dead-time
compensation of 833 ns
Using the specified values from Section 14.
“High-Speed PWM” (DS70645):
“High-Speed PWM” (DS70645):
• PHASEx = 1000
• PDCx = 500
• ALTDTR = 833 ns/8.33 ns = 100
• DTR = (833 ns/8.33 ns)/2 = 50
Applying the work around:
• ALTDTR = 2 * 100 = 200
• PDCx = PDCx – 25 = 475
Affected Families and Silicon Revisions
12. Module: Flash
The stall mechanism may not function properly
when erasing or programming Flash memory.
when erasing or programming Flash memory.
Work around
Disable interrupts until the erase or programming
operation is complete. Test for completion by
inserting a bit test operation of the Write Control
(WR) bit.
operation is complete. Test for completion by
inserting a bit test operation of the Write Control
(WR) bit.
Code is provided in
that can be used to
disable interrupts during RTSP erase/program
operations.
operations.
EXAMPLE 1:
WORK AROUND CODE
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
; Load write latches if programming
…
; Setup NVMCON register to erase or program
as required
…
; Disable interrupts
PUSH
SR
MOV
#0x00E0, W0
IOR
SR
; Write the KEY sequence
MOV
#0x55, W0
MOV
W0, NVMKEY
MOV
#0xAA, W0
MOV
W0, NVMKEY
; Start the programming sequence
BSET
NVMCON, #15
; Insert two NOPs after programming
NOP
NOP
; Wait for operation to complete
prog_wait:
BTSC
NVMCON, #15
BRA
prog_wait
; Re-enable interrupts,
POP
SR