Microchip Technology MA330028 데이터 시트
2011-2014 Microchip Technology Inc.
DS80000533H-page 15
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
23. Module: CPU
An unexpected address error trap may occur
during accesses to program memory addresses,
0x001 through 0x200. This has been observed
when one or more interrupt requests are asserted
while reading or writing program memory
addresses, using TBLRDx, TBLWTx or PSV-based
instructions.
during accesses to program memory addresses,
0x001 through 0x200. This has been observed
when one or more interrupt requests are asserted
while reading or writing program memory
addresses, using TBLRDx, TBLWTx or PSV-based
instructions.
Work around
Before executing instructions that read or write
program memory addresses, 0x001 through
0x200, disable interrupts using the DISI
instruction.
program memory addresses, 0x001 through
0x200, disable interrupts using the DISI
instruction.
Affected Families and Silicon Revisions
24. Module: PWM
In Center-Aligned mode, updates to active
MDC/PDCx/ALTDTRx/PHASEx registers occur
only once every two PWM periods; that is, when
the PWM timer matches the PHASEx register. In
other words, the double update feature is not
available.
MDC/PDCx/ALTDTRx/PHASEx registers occur
only once every two PWM periods; that is, when
the PWM timer matches the PHASEx register. In
other words, the double update feature is not
available.
illustrates this relationship.
Work around
None.
Affected Families and Silicon Revisions
FIGURE 2:
PWM TIMING DIAGRAM
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
—
PHASEx
Period
Update
Update
0
2x Period
PWMxH
PWMxL
PTMRx