Microchip Technology MA330018 데이터 시트
© 2007-2012 Microchip Technology Inc.
DS70291G-page 83
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
6.3
System Reset
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC Configuration bits in the FOSC device
Configuration register selects the device clock source.
X04 and dsPIC33FJ128MCX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC Configuration bits in the FOSC device
Configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The description of
the sequence in which this occurs is shown in
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The description of
the sequence in which this occurs is shown in
TABLE 6-1:
OSCILLATOR DELAY
Oscillator Mode
Oscillator
Startup Delay
Oscillator
Startup Timer
PLL Lock Time
Total Delay
FRC, FRCDIV16, FRCDIVN
T
OSCD
—
—
T
OSCD
FRCPLL
T
OSCD
—
T
LOCK
T
OSCD
+ T
LOCK
XT
T
OSCD
T
OST
—
T
OSCD
+ T
OST
HS
T
OSCD
T
OST
—
T
OSCD
+ T
OST
EC
—
—
—
—
XTPLL
T
OSCD
T
OST
T
LOCK
T
OSCD
+ T
OST
+
T
LOCK
HSPLL
T
OSCD
T
OST
T
LOCK
T
OSCD
+ T
OST
+
T
LOCK
ECPLL
—
—
T
LOCK
T
LOCK
S
OSC
T
OSCD
T
OST
—
T
OSCD
+ T
OST
LPRC
T
OSCD
—
—
T
OSCD
Note 1: T
OSCD
= Oscillator Start-up Delay (1.1
μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: T
OST
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OST
= 102.4
μs for a
10 MHz crystal and T
OST
= 32 ms for a 32 kHz crystal.
3: T
LOCK
= PLL lock time (1.5 ms nominal), if PLL is enabled.