Microchip Technology DM160214 데이터 시트

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DS41414D-page 473

PIC16(L)F1946/47

Asynchronous Transmission (Back to Back) ............ 301
Auto Wake-up Bit (WUE) During Normal Operation . 316
Auto Wake-up Bit (WUE) During Sleep .................... 316
Automatic Baud Rate Calculator............................... 315
Baud Rate Generator with Clock Arbitration ............. 275
BRG Reset Due to SDA Arbitration During Start

Condition........................................................... 286

Brown-out Reset (BOR) ............................................ 407
Brown-out Reset Situations ........................................ 81
Bus Collision During a Repeated Start Condition

(Case 1) ............................................................ 287

Bus Collision During a Repeated Start Condition

(Case 2) ............................................................ 287

Bus Collision During a Start Condition (SCL = 0) ..... 286
Bus Collision During a Stop Condition (Case 1) ....... 288
Bus Collision During a Stop Condition (Case 2) ....... 288
Bus Collision During Start Condition (SDA only) ...... 285
Bus Collision for Transmit and Acknowledge............ 284
CLKOUT and I/O....................................................... 405
Clock Synchronization .............................................. 272
Clock Timing ............................................................. 404
Comparator Output ................................................... 179
Enhanced Capture/Compare/PWM (ECCP) ............. 409
Fail-Safe Clock Monitor (FSCM) ................................. 74
First Start Bit Timing ................................................. 276
Full-Bridge PWM Output ........................................... 229
Half-Bridge PWM Output .................................. 227, 234
I

2

C Bus Data ............................................................. 417

I

2

C Bus Start/Stop Bits.............................................. 416

I

2

C Master Mode (7 or 10-Bit Transmission) ............ 279

I

2

C Master Mode (7-Bit Reception)........................... 281

I

2

C Stop Condition Receive or Transmit Mode ......... 283

INT Pin Interrupt.......................................................... 90
Internal Oscillator Switch Timing................................. 69
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 364
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 366
PWM Auto-shutdown ................................................ 233

Firmware Restart .............................................. 233

PWM Direction Change ............................................ 230
PWM Direction Change at Near 100% Duty Cycle ... 231
PWM Output (Active-High)........................................ 225
PWM Output (Active-Low) ........................................ 226
Repeat Start Condition.............................................. 277
Reset Start-up Sequence............................................ 83
Reset, WDT, OST and Power-up Timer ................... 406
Send Break Character Sequence ............................. 317
SPI Master Mode (CKE = 1, SMP = 1) ..................... 414
SPI Mode (Master Mode).......................................... 249
SPI Slave Mode (CKE = 0) ....................................... 415
SPI Slave Mode (CKE = 1) ....................................... 415
Synchronous Reception (Master Mode, SREN) ....... 322
Synchronous Transmission....................................... 319
Synchronous Transmission (Through TXEN) ........... 319
Timer0 and Timer1 External Clock ........................... 408
Timer1 Incrementing Edge........................................ 203
Two-Speed Start-up.................................................... 72
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 353
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 355
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 357
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 359
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 361
Type-A/Type-B in Static Drive................................... 352
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 354
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 356
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 358

Type-B in 1/3 MUX, 1/3 Bias Drive........................... 360
Type-B in 1/4 MUX, 1/3 Bias Drive........................... 362
USART Synchronous Receive (Master/Slave) ......... 413
USART Synchronous Transmission (Master/Slave). 412
Wake-up from Interrupt............................................. 106

Timing Diagrams and Specifications

PLL Clock ................................................................. 405

Timing Parameter Symbology .......................................... 403
Timing Requirements

I

C Bus Data............................................................. 418

I2C Bus Start/Stop Bits............................................. 417
SPI Mode.................................................................. 416

TMR0 Register.................................................................... 33
TMR1H Register ................................................................. 33
TMR1L Register.................................................................. 33
TMR2 Register.............................................................. 33, 4 1
TRIS ................................................................................. 388
TRISA Register........................................................... 34, 1 31
TRISB Register........................................................... 34, 1 34
TRISC............................................................................... 136
TRISC Register........................................................... 34, 137
TRISD............................................................................... 139
TRISD Register........................................................... 34, 140
TRISE ............................................................................... 142
TRISE Register........................................................... 34, 1 43
TRISF ............................................................................... 145
TRISF Register ........................................................... 39, 1 46
TRISG............................................................................... 148
TRISG Register .......................................................... 39, 1 49
Two-Speed Clock Start-up Mode........................................ 71
TX2REG Register ............................................................... 42
TX2STA Register................................................................ 42
TXCON (Timer2/4/6) Register .......................................... 213
TXxREG ........................................................................... 299
TXxREG Register ............................................................... 36
TXxSTA Register ........................................................ 36, 307

BRGH Bit .................................................................. 310

U

USART

Synchronous Master Mode

Requirements, Synchronous Receive .............. 413
Requirements, Synchronous Transmission...... 413
Timing Diagram, Synchronous Receive ........... 413
Timing Diagram, Synchronous Transmission... 412

V

REF

. S

EE

ADC Reference Voltage

W

Wake-up on Break ............................................................ 315
Wake-up Using Interrupts ................................................. 106
Watchdog Timer (WDT)...................................................... 82

Associated Registers................................................ 110
Configuration Word w/ Watchdog Timer................... 110
Modes....................................................................... 108
Specifications ........................................................... 408

WCOL....................................................... 275, 278, 2 80, 2 82
WCOL Status Flag.................................... 275, 278, 2 80, 2 82
WDTCON Register ........................................................... 109
WPUB Register................................................................. 135
WPUG Register ................................................................ 150
Write Protection .................................................................. 59
WWW Address ................................................................. 475
WWW, On-Line Support ....................................................... 9