Microchip Technology MA330019 데이터 시트

© 2007-2012 Microchip Technology Inc.

DS70291G-page  143

The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 oscillator system 
provides:

• External and internal oscillator options as clock 

sources

• An on-chip Phase-Locked Loop (PLL) to scale the 

internal operating frequency to the required 
system clock frequency

• An internal FRC oscillator that can also be used 

with the PLL, thereby allowing full-speed 
operation without any external clock generation 
hardware

• Clock switching between various clock sources
• Programmable clock postscaler for system power 

savings

• A Fail-Safe Clock Monitor (FSCM) that detects 

clock failure and takes fail-safe measures

• An Oscillator Control register (OSCCON)
• Non-volatile Configuration bits for main oscillator 

selection

• An auxiliary crystal oscillator for audio DAC
A simplified diagram of the oscillator system is shown 
in 

.

Note 1: This data sheet summarizes the features 

of the dsPIC33FJ32MC302/304, 
dsPIC33FJ64MCX02/X04 and 
dsPIC33FJ128MCX02/X04 family of 
devices. It is not intended to be a 
comprehensive reference source. To 
complement the information in this data 
sheet, refer to Section 39. “Oscillator 
(Part III)” (DS70216) of the “dsPIC33F/
PIC24H Family Reference Manual”, 
which is available from the Microchip web 
site (

www.microchip.com

).

2: Some registers and associated bits 

described in this section may not be 
available on all devices. Refer to 

 in 

this data sheet for device-specific register 
and bit information.

See 

 for PLL details.

If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M

Ω must be connected.

The term F

P

 refers to the clock source for all the peripherals, while F

CY

 refers to the clock source for the CPU. Throughout this 

document F

CY

 and F

P

 are used interchangeably, except in the case of Doze mode. F

P

 and F

CY

 will be different when Doze mode 

is used in any ratio other than 1:1, which is the default.

Secondary Oscillator

LPOSCEN

SOSCO

SOSCI

Timer1

XTPLL, HSPLL,

XT, HS, EC

FRCDIV<2:0> 

PWRT, 

FSCM

FRCDIVN

S

OSC

FRCDIV16

ECPLL, FRCPLL

NOSC<2:0>

FNOSC<2:0>

Reset

FRC

Oscillator

LPRC

Oscillator

DOZE<2:0>

S3

S1

S2

S1/S3

S7

S6

FRC 

LPRC

S0

S5

S4

÷ 16

Clock Switch

S7

Clock Fail

÷ 2

TUN<5:0>

PLL

F

CY(3)

F

OSC

FR

CDIV

DOZE

÷ N

ACLK

POSCCLK

Auxiliary Oscillator

SELACK

APSTSCLR<2:0> 

DAC

F

OSC(1)

AOSCCLK

AOSCMD<1:0>

ASRCSEL

F

OSC(1)

POSCCLK

OSC2

OSC1

Primary Oscillator

R

POSCMD<1:0>

F

P(3)

WDT, 

3.5 MHz 

≤ AUX_OSC_F

IN

 

≤ 10 MHz

1

0

0

1