Microchip Technology MA330019 데이터 시트
© 2007-2012 Microchip Technology Inc.
DS70291G-page 29
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
bit 1
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER (CONTINUED)
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.