Microchip Technology MA330012 데이터 시트

DS70165E-page 138

©

 2007 Microchip Technology Inc.

7.2.5

CONTINUOUS OR ONE-SHOT 
OPERATION

Each DMA channel can be configured for One-Shot or
Continuous mode operation. 

If MODE<0> (DMAxCON<0>) is clear, the channel
operates in Continuous mode.

When all data has been moved (i.e., buffer end has
been detected), the channel is automatically reconfig-
ured for subsequent use. During the last data transfer,
the next Effective Address generated will be the origi-
nal start address (from the selected DMAxSTA or
DMAxSTB register). If the HALF bit (DMAxCON<12>)
is clear, the transfer complete interrupt flag (DMAxIF)
is set. If the HALF bit is set,  DMAxIF will not be set at
this time and the channel will remain enabled.

If MODE<0> is set, the channel operates in One-Shot
mode. When all data has been moved (i.e., buffer end
has been detected), the channel is automatically dis-
abled. During the last data transfer, no new Effective
Address is generated and the DMA RAM Address
register retains the last DMA RAM address that was
accessed. If the HALF bit is clear, the DMAxIF bit is
set. If the HALF bit is set, the DMAxIF will not be set at
this time and the channel is automatically disabled. 

7.2.6

PING-PONG MODE

When the MODE<1> bit (DMAxCON<1>) is set by the
user, Ping-Pong mode is enabled. 

In this mode, successive block transfers alternately
select DMAxSTA and DMAxSTB as the DMA RAM
start address. In this way, a single DMA channel can
be used to support two buffers of the same length in
DMA RAM. Using this technique maximizes data
throughput by allowing the CPU time to process one
buffer while the other is being loaded.

7.2.7

MANUAL TRANSFER MODE

A manual DMA request can be created by setting the
FORCE bit (DMAxREQ<15>) in software. If already
enabled, the corresponding DMA channel executes a
single data element transfer rather than a block transfer

The FORCE bit is cleared by hardware when the
forced DMA transfer is complete and cannot be
cleared by the user. Any attempt to set this bit prior to
completion of a DMA request that is underway will
have no effect.

The manual DMA transfer function is a one-time event.
The DMA channel always reverts to normal operation
(i.e., based on hardware DMA requests) after a forced
(manual) transfer.

This mode provides the user a straightforward method
of initiating a block transfer. For example, using
Manual mode to transfer the first data element into a
serial peripheral allows subsequent data within the
buffer to be moved automatically by the DMAC using a
‘transmit buffer empty’ DMA request.

7.2.8

DMA REQUEST SOURCE 
SELECTION

Each DMA channel can select between one of 128
interrupt sources to be a DMA request for that chan-
nel, based on the contents of the IRQSEL<6:0> bits
(DMAxREQ<6:0>). The available interrupt sources are
device dependent. Please refer to Table 7-1 for IRQ
numbers associated with each of the interrupt sources
that can generate a DMA transfer.

Each DMA channel can generate an independent
‘block transfer complete’ (HALF = 

0

) or ‘half block

transfer complete’ (HALF = 

1

) interrupt. Every DMA

channel has its own interrupt vector and therefore,
does not use the interrupt vector of the peripheral to
which it is assigned. If a peripheral contains multi-word
buffers, the buffering function must be disabled in the
peripheral in order to use DMA. DMA interrupt
requests are only generated by data transfers and not
by peripheral error conditions. 

The DMA controller can also react to peripheral and
DMA RAM write collision error conditions through a
nonmaskable CPU trap event. A DMA error trap is
generated in either of the following Fault conditions:

• DMA RAM data write collision between the CPU 

and a peripheral

- This condition occurs when the CPU and a 

peripheral attempt to write to the same DMA 
RAM address simultaneously

• Peripheral SFR data write collision between the 

CPU and the DMA controller

- This condition occurs when the CPU and the 

DMA controller attempt to write to the same 
peripheral SFR simultaneously

The channel DMA RAM and peripheral write collision
Faults are combined into a single DMAC error trap
(Level 10) and are nonmaskable. Each channel has
DMA RAM Write Collision (XWCOLx) and Peripheral
Write Collision (PWCOLx) status bits in the DMAC
Status register  (DMACS) to allow the DMAC error trap
handler to determine the source of the Fault condition.