Microchip Technology MA330012 데이터 시트
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 217
dsPIC33F
REGISTER 18-1:
I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-1 HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0 HC
R/W-0 HC
R/W-0 HC
R/W-0 HC
R/W-0 HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Set in hardware
HC = Cleared in hardware
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1
= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0
= Disables the I2Cx module. All I
2
C pins are controlled by port functions.
bit 14
Unimplemented: Read as ‘
0
’
bit 13
I2CSIDL: Stop in Idle Mode bit
1
= Discontinue module operation when device enters an Idle mode
0
= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I
2
C slave)
1
= Release SCLx clock
0
= Hold SCLx clock low (clock stretch)
If STREN =
1
:
Bit is R/W (i.e., software may write ‘
0
’ to initiate stretch and write ‘
1
’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN =
0
:
Bit is R/S (i.e., software may only write ‘
1
’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1
= IPMI mode is enabled; all addresses Acknowledged
0
= IPMI mode disabled
bit 10
A10M: 10-bit Slave Address bit
1
= I2CxADD is a 10-bit slave address
0
= I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1
= Slew rate control disabled
0
= Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1
= Enable I/O pin thresholds compliant with SMBus specification
0
= Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I
2
C slave)
1
= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0
= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with SCLREL bit.
1
= Enable software or receive clock stretching
0
= Disable software or receive clock stretching