Microchip Technology MA330012 데이터 시트
dsPIC33F
DS70165E-page 24
Preliminary
©
2007 Microchip Technology Inc.
FIGURE 1-1:
dsPIC33F GENERAL BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
V
DDCORE
/V
CAP
UART1,2
ECAN1,2
PWM
DCI
IC1-8
OC/
SPI1,2
I2C1,2
QEI
PORTA
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
and features present on each device.
PWM1-8
CN1-23
Instruction
Decode &
Control
PCH PCL
16
Program Counter
16-bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
Address Bus
Li
ter
a
l D
a
ta
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
DMA
RAM
DMA
Controller
Control Signals
to Various Blocks
to Various Blocks
ADC1,2
Timers
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Address Generator Units
1-9