Microchip Technology MA330012 데이터 시트
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 79
dsPIC33F
REGISTER 4-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0
(1)
R/W-0
(1)
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
(1)
U-0
U-0
R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
—
ERASE
—
—
NVMOP<3:0>
(2)
bit 7
bit 0
Legend:
SO = Satiable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1
= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0
= Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1
= Enable Flash program/erase operations
0
= Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1
= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0
= The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘
0
’
bit 6
ERASE: Erase/Program Enable bit
1
= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0
= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
Unimplemented: Read as ‘
0
’
bit 3-0
NVMOP<3:0>: NVM Operation Select bits
(2)
1111
= Memory bulk erase operation (ERASE =
1
) or no operation (ERASE =
0
)
1110
= Reserved
1101
= Erase General Segment and FGS Configuration register
(ERASE = 1) or no operation (ERASE = 0)
1100
= Erase Secure Segment and FSS Configuration register
(ERASE = 1) or no operation (ERASE = 0)
1011
= Reserved
0011
= Memory word program operation (ERASE =
0
) or no operation (ERASE =
1
)
0010
= Memory page erase operation (ERASE =
1
) or no operation (ERASE =
0
)
0001
= Memory row program operation (ERASE =
0
) or no operation (ERASE =
1
)
0000
= Program or erase a single Configuration register byte
Note 1:
These bits can only be reset on POR.
2:
All other combinations of NVMOP<3:0> are unimplemented.