Microchip Technology MA330016 데이터 시트

다운로드
페이지 300
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 174
© 2007-2011 Microchip Technology Inc.
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0 = Address Detect mode disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1
→0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
REGISTER 17-2:
U
x
STA: UART
x
 STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for 
information on enabling the UART module for transmit operation.