Microchip Technology MCP3421DM-WS 데이터 시트
PIC18F2455/2550/4455/4550
DS39632E-page 70
© 2009 Microchip Technology Inc.
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0100 q000
HLVDCON
VDIRMAG
—
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
0-00 0101
WDTCON
—
—
—
—
—
—
—
SWDTEN
--- ---0
RCON
IPEN
SBOREN
(2)
—
RI
TO
PD
POR
BOR
0q-1 11q0
TMR1H
Timer1 Register High Byte
xxxx xxxx
TMR1L
Timer1 Register Low Byte
xxxx xxxx
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
TMR2
Timer2 Register
0000 0000
PR2
Timer2 Period Register
1111 1111
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
SSPBUF
MSSP Receive Buffer/Transmit Register
SSPADD
MSSP Address Register in I
2
C™ Slave mode. MSSP Baud Rate Reload Register in I
2
C™ Master mode.
0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPCON2
GCEN
ACKSTAT
ACKDT/
ADMSK5
(7)
ACKEN/
ADMSK4
(7)
RCEN/
ADMSK3
(7)
PEN/
ADMSK2
(7)
RSEN/
ADMSK1
(7)
SEN
0000 0000
ADRESH
A/D Result Register High Byte
xxxx xxxx
ADRESL
A/D Result Register Low Byte
xxxx xxxx
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0qqq
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0-00 0000
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
CCP1CON
P1M1
(3)
P1M0
(3)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
BAUDCON
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
0100 0-00
ECCP1DEL
PRSEN
PDC6
(3)
PDC5
(3)
PDC4
(3)
PDC3
(3)
PDC2
(3)
PDC1
(3)
PDC0
(3)
0000 0000
ECCP1AS
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
(3)
PSSBD0
(3)
0000 0000
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
TMR3H
Timer3 Register High Byte
xxxx xxxx
TMR3L
Timer3 Register Low Byte
xxxx xxxx
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
SPBRGH
EUSART Baud Rate Generator Register High Byte
0000 0000
SPBRG
EUSART Baud Rate Generator Register Low Byte
0000 0000
RCREG
EUSART Receive Register
0000 0000
TXREG
EUSART Transmit Register
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
TABLE 5-2:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note
1:
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5:
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6:
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7:
I
2
C™ Slave mode only.