Microchip Technology DM164134 데이터 시트
PIC18FXX8
DS41159E-page 100
© 2006 Microchip Technology Inc.
9.3
PORTC, TRISC and LATC
Registers
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
EXAMPLE 9-3:
INITIALIZING PORTC
FIGURE 9-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISC
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
Peripheral Out Select
Data Bus
WR LATC
WR TRISC
Data Latch
TRIS Latch
RD TRISC
Q
D
Q
CK
Q
D
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
V
DD
V
SS
RD PORTC
Peripheral Data In
I/O pin
(1)
or
WR PORTC
WR PORTC
RD LATC
Schmitt
Trigger
Trigger
Note
1: I/O pins have diode protection to V
DD
and V
SS
.
TRIS
Override
Peripheral Enable
TRIS OVERRIDE
Pin
Override
Peripheral
RC0
Yes
Timer1 Oscillator
for Timer1/Timer3
for Timer1/Timer3
RC1
Yes
Timer1 Oscillator
for Timer1/Timer3
for Timer1/Timer3
RC2
No
—
RC3
Yes
SPI™/I
2
C™
Master Clock
RC4
Yes
I
2
C Data Out
RC5
Yes
SPI Data Out
RC6
Yes
USART Async
Xmit, Sync Clock
Xmit, Sync Clock
RC7
Yes
USART Sync Data
Out
Out