Microchip Technology DM164134 데이터 시트

DS41159E-page 120

© 2006 Microchip Technology Inc.

Timer3 can operate in one of these modes:

• As  a  timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).

When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.

When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored. 

Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).

TMR3H

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN

Enable

Oscillator

TMR3IF
Overflow
Interrupt

F

OSC

/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

1

0

0

1

Synchronized

Clock Input

2

T1OSO/

T1OSI

Flag bit

1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T1CKI

CCP Special Trigger

T3CCPx

CLR

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN

Enable
Oscillator

F

OSC

/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

1

0

0

1

Synchronized

Clock Input

2

T1OSO/

T1OSI

TMR3

T1CKI

CLR

CCP Special Trigger

T3CCPx

To Timer1 Clock Input

1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

TMR3H

Data Bus<7:0>

8

TMR3H

8

8

8

Read TMR3L

Write TMR3L

TMR3IF Overflow
Interrupt Flag
bit