Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors

18

Freescale Semiconductor, Inc.

Tests are conducted using the input levels specified in 

Table 5 on page 15

. Unless otherwise specified, propagation delays are 

measured from the 50-percent to 50-percent point. Rise and fall times are measured between the 10-percent and 90-percent 
points, as shown in the following figure.

The subsequent figure shows the definitions of the following signal states:

• Active state, when a bus or signal is driven and enters a low-impedance state
• Three-stated, when a bus or signal is placed in a high-impedance state
• Data Valid state, when a signal level has reached V

OL

 or V

OH

• Data Invalid state, when a signal level is in transition between V

OL

 and V

OH

1.

All conditions at nominal supply: V

DD

 = V

DDA

 = 1.8 V

V

DD

 rise time

T

rvdd

10% to 90%

—

—

1

ms

POR release delay

(2)

2.

This is the time measured from V

DD

 = V

POR

 until the internal reset signal is released.

T

POR

Power-up

0.35

1.5

ms

Warm-up time

T

WU

From STOP

NC

—

7

—

sample 
periods

Frequency of operation

F

OPH

Full Speed Clock

—

8

—

MHz

F

OPL

Slow Clock

—

62.5

—

KHz

System clock period

t

CYCH

Full Speed Clock

—

125

—

ns

t

CYCL

Slow Clock

—

16

—

s

Full/Slow clock ratio

—

—

—

128

—

Oscillator frequency absolute accuracy @ 25°C

—

Full Speed Clock

-5

— 

+5

%

Oscillator frequency variation over temperature
(-40°C to 85°C vs. ambient)

—

Slow  Clock

-6

—

+6

%

Minimum RESET assertion duration

t

RA

—

4T

(3)

3.

In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 

s.

—

—

—

V

IH

V

IL

Fall Time

Input Signal

Note: The midpoint is V

IL

 + (V

IH

 – V

IL

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

Data Invalid State

Data1

Data

3-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

Data Active

Data1 Valid